研究生: |
簡伯諺 Po-Yen Chien |
---|---|
論文名稱: |
鉬金屬閘極金氧半元件之電性研究 Investigation of electrical characteristics for MOS devices with Molybdenum metal gate |
指導教授: | 張廖貴術 |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
原子科學院 - 工程與系統科學系 Department of Engineering and System Science |
論文出版年: | 2007 |
畢業學年度: | 95 |
語文別: | 英文 |
論文頁數: | 104 |
中文關鍵詞: | 鉬 、金屬閘極 |
相關次數: | 點閱:76 下載:0 |
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傳統電晶體製程使用多晶矽當作閘極材料已經行之多年。然而,由於通道長度跟閘極界電層的厚度快速的微縮,多晶矽的使用已經面臨了許多問題。例如:閘極空乏區的產生,較高的閘極片電阻,較大的閘極穿遂電流以及在製作時,硼離子穿透到通道的可能性大增。因此,使用金屬閘極與高介電常數的介電層取代多晶矽與矽氧化層已經成為不可避免的趨勢。
在這篇論文裡頭,我們製作了一個具有高功函數且可接受的電性的金屬閘極,在考慮到所有電性之下,我們發現氮化鉬(2.4)擁有較好的電性與較高的功函數,例如在遲滯現象,電應力引起的漏電流上升,電應力引起的平帶電壓偏移都有較佳的表現。
除此之外,氮化鈦插入氮化鉬的上層與下層組成不同的金屬閘極堆疊也被拿來討論。而我們發現,將氮化鈦插入氮化鉬的下層能夠有效的改善所有的電性能力,即使這樣子堆疊之後,功函數有下降一點的趨勢。這結果代表的是,將氮化鈦插入氮化鉬的下面比插入上面要來的好,並且可以當作一個讓P型金氧半電晶體使用的金屬閘極。
最後,金屬閘極與高介電常數介電層的組合也被拿來討論。我們採用氮化鈦插入氮化鉬下面的金屬堆疊當作金屬閘極,常見的氮氧化鉿當作高介電常數介電層,一起組合起來探討其電性與熱穩定性的好壞。而實驗結果發現,這樣的搭配擁有小的等效氧化層厚度與可接受的電性能力,除此之外,也能達到可接受的熱穩定性。
Traditional transistor processes use poly-Si as gate material for decades. However, aggressive scaling of channel length and gate oxide thickness in a conventional transistor aggravates the problems of poly-silicon (poly-Si) gate depletion, high gate resistance, high gate tunneling leakage current, and boron penetration into the channel region. As a result, there is immense interest in metal gates and alternative gate dielectrics with higher permittivity.
In this work we developed a good metal gate with high work function and acceptable electrical characteristics. By considering all the electrical characteristics, we find that Mo0.9N0.1 (=MoN(2.4)) shows higher work function and better electrical characteristics such as hysteresis, SILC, stress induced charge trapping.
Moreover, the differences of MoN metal gate inserting TiN layer in different position were compared. Metal gate with MoN/TiN film exhibits better performance for all the electrical characteristics despite a little lower WF. The results show that MoN/TiN metal gate electrode is better than TiN/MoN metal one and it can be a promising candidate for MOS device applications.
Finally, the integration of metal gate and high-k dielectric was investigated. MoN/TiN and HfOxNy were selected as the metal gate and gate dielectric candidates to study the electrical characteristics and thermal stability. The experimental results show that thin EOT and acceptable electrical characteristics are observed in MoN/TiN/HfOxNy MOS device. Furthermore, acceptable thermal stability is also achieved.
[I] J. R. Hauser et al., 1997 SRC working paper
[2] You-Seok Suh et al., Electrical Characteristics of TaSixNy Gate Electrodes For Dual Gate Si-CMOS Devices 2001, Symposium on VLSl Technology Digest of Technical Papers p.47
[3] L. Chang et al., 2000, “Gate length scaling and threshold voltage control of double-gate MOSFETs,” in IEDM Tech. Dig., pp. 719–722
[4] De et al, 2000, Solid-state Electronics, vol 44, p.1077
[5] Q. Lu, Y. C. Yeo, P. Ranade, H. Takeuchi, T. J. King, and C. Hu, 2000, “Dual metal gate technology for deep-submicron CMOS transistors,” in Symp. VLSI Tech. Dig., pp. 72–73
[6] R. M. Wallace 2002, at U. North Texas
[7] Hsin-Chun Chang, Integration of metal gate and high-k gate dielectric for advanced MOS devices 2006, thesis in the department of engineering and system science NTHU p.11
[8] P. Ranade et al., 2002, “Tunable work function molybdenum gate technology for FDSOI-CMOS,” in IEDM Tech. Dig., pp. 363–366
[9] Tzung-Lin Li et al., June, 2005, Continuous and Precise Work Function Adjustment for Integratable Dual Metal Gate CMOS Technology Using Hf–Mo Binary Alloys IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 6
[10] You-Seok Suh et al., JULY 2003, “Effect of the Composition on the Electrical Properties of TaSixNy Metal Gate Electrodes” IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 7
[11] B. Travel et al., 2001, iedm p.825
[12] Q. Xing et al., 2003, VLSI p.101
[13] H. Zhong et al., 2001, “Properties of Ru-Ta alloys as gate electrodes for nMOS and pMOS silicon devices,” in IEDM Tech. Dig., pp. 467–480
[14] J. Lee et al., 2002, “Tunable work function dual metal gate technology for bulk and nonbulk CMOS,” in IEDM Tech. Dig., pp. 359–362
[15] B.-Y. Tsui et al., Mar. 2003, “Wide range work function modulation of binary alloys for MOSFET application,” IEEE Electron Device Lett., vol. 24, no. 3, pp. 153–155
[16] S. H. Bae et al., 2004, “Laminated metal gate electrode with tunable work function for advanced CMOS,” in Symp. VLSI Tech. Dig., pp. 188–189.
[17] Stefan De Gendt, 2004, IEDM Short Course, IMEC
[18] Z. Zhang 2005, at SEMATECH
[19] Chatterjee et al., 1997, iedm; C. Ren et al., 2004, EDL; B. Doris et al., 2005 VLSI-TSA
[20] Y.-C. Yeo, et al., 2002, JAP p. 7266
[21] C. Hobbs, et al., 2003, Symp. VLSI Tech. Dig., p.9
[22] C. Hobbs, et al., 2004, Trans. Elec. Dev. Lett., vol.51(6), p.971
[23] C. Wang, et al., 2003, Appl. Phys. Lett., vol.83 (2), p.308
[24] H.Y. Yu, et al., 2004, TED p.337
[25] Mark Rodder, 2004, IEDM Short Course, Texas Instrument.
[26] H.F. Luan et al. 1999, IEDM Tech. Dig, p.99
[27] H. Ono, et al., 1998, Appl. Phys. Lett., vol.73, no.11, p.1517
[28] R. Beyers, 1984, J. of Appl. Phys., vol.56, p.1
[29] W. Zhu, et al., 2004, Trans. Elec. Dev. Lett., vol.51 (1), p.98
[30] M. V. Fischetti, et al., 2001, J. Appl. Phys., vol.90 (9), p.4587
[31] Robert Chau, et al., 2004, Elec. Dev. Lett., vol.25 (6), p.408
[32] Hsin-Chun Chang, Integration of metal gate and high-k gate dielectric for advanced MOS devices 2006, thesis in the department of engineering and system science NTHU p.18-20
[33] V. Misra, et al., 2002, MRS bulletin, vol.27, no.3, p.212
[34] Hsin-Chun Chang, Integration of metal gate and high-k gate dielectric for advanced MOS devices 2006, thesis in the department of engineering and system science NTHU p.11-12
[35] H. Fujioka, et al., “QMCV simulator” online available http://www-device.eecs.berkeley.edu/qmcv/index.html
[36] S. Zafar, et al., 2002, Applied Physics Letters, vol.81, pp.2608-2610
[37] D. J. DiMaria, et al., Sep. 1995, J. Appl. Phys., vol.78, no.6, pp.3883-3894, 15
[38] S. I. Takagi, et al., 1996, IEDM Tech. Dig., pp.323-326
[39] E. Rosenbaum, et al., 1997, IEEE Trans. Electron Devices, vol.44, no.2, pp.317-323
[40] S. Zafar, et al., Jun. 2002, APL., vol 80, number 25, pp.4858-4860
[41] Huang-Chun Wen et al., July 2006, IEEE EDL, vol.27, no.7 pp.598-601
[42] D. K. Schroder, 1998, Semiconductor Material and Device Characterization, 2nd ed., John Wiley & Sons, New York
[43] N. V. Nguyen, et al., 2000, Appl. Phys. Lett., 77, 3012
[44] P. T. Gao, et al., 2000, Thin Solid Films, 377, 557
[45] K. Kukli, et al., 1995, Thin Solid Films, 260, 135
[46] M. Cassir, et al., 2002, Appl. Surf. Sci., 193, 120
[47] C. M. Perkins, et al., 2001, Appl. Phys. Lett., 78, 2357
[48] C. Chaneliere, et al., Microelectron. Reliab., 39, 261 (1999)
[49] D. D. L. Chung, et al., 1993, X-Ray Diffraction at Elevated Temperatures: A Method for In-Situ Process Analysis, Chap.1, VCH Publishers, New York
[50] Powder Diffraction File: Inorganic and Organic Data Book, PDF#19-1299, 25-0922, 25-1257, 25-1366, 27-1402, 34-1084, 42-0060, 42-1120, and 72-1088, JCPDS – International Center for Diffraction Data, American Society for Testing and Materials, Swarthmore, PA (1950-2003)
[51] Y. Nishi, et al., 2000, Handbook of Semiconductor Manufacturing Technology, Chap.28, Marcel Dekker, New York
[52] B. Maiti, et al., 1998, IEDM Tech. Dig., pp.781-784
[53] Tsu-Tae King et al., 1998, “novel material and processes for MOS devices, final report for MICRO Project”, p.71
[54] VLSI Elec. Microstructure Sci. 9 (Academic Press 1985)
[55] H.C. Chang, “Integration of metal gate and high-k gate dielectric for advanced MOS devices” Institute of ESS NTHU 2006, p.145
[56] B. Y. Tsui, et al., Journal of Electrochemical Society 2006, vol.153, pp. G197-G202
[57] H. B. Michaelson, 1977,J. Appl. Phys., vol.48, p.4729
[58] R. Lin, et al., 2002, IEEE Electron Device Lett., vol.23, p.49
[59] Y.-K. Choi, et al., 2002, Tech. Dig. - Int. Electron Devices Meet., 259
[60] Q. Lu, et al., 2001, in Proceedings of the IEEE Symposium on VLSI Technology, p. 45
[61] P. Ranade, et al., 2001, Electrochem. Solid-State Lett., 4, G85
[62] Robert O’Connor et al., 2005, Semi. Sci. Technol., 20, 668-672
[63] X.Sun et al., Dec. 1993, Thin Solid Film, vol.236, p. no1/2
[64] Stanley Wolf, 1990, Silicon Processing for the VLSI ERA, vol.2, Lattice Press, California
[65] T. Hara et al., Materials for Advanced Metallization, Poster session II
[66] Rashmi Jha et al., 2005, APL, 87 223503