RAMSES-D:支援延遲錯誤與權重耦合錯誤的動態記憶體錯誤模擬器

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研究生：	巫松洸 Song-Guang Wu
論文名稱：	RAMSES-D:支援延遲錯誤與權重耦合錯誤的動態記憶體錯誤模擬器 RAMSES-D: DRAM Fault Simulator Supporting Delay Fault and Weighted Coupling Fault
指導教授：	吳誠文 Cheng-Wen Wu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	49
中文關鍵詞：	記憶體錯誤模擬、記憶體延遲錯誤、耦合錯誤
外文關鍵詞：	memory fault simulation, memeory delay fault, coupling fault
相關次數：	點閱：92 下載：0
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記憶體錯誤模擬器是驗證記憶體測試樣本的重要工具。其功能為驗證測試樣本的錯誤覆蓋率，並協助測試樣本最佳化；另外能夠提供測試簽名，縮小記憶體錯誤可能發生的情況，協助使用者進行錯誤診斷。我們在過去曾發展出一套記憶體錯誤模擬器，稱為RAMSES (Random Access Memory Simulator for Error Screening)。RAMSES使用了 ”錯誤描述器” 的觀念，修改了錯誤模擬的流程，並能支援新增加的錯誤模型。
延遲錯誤在近代的測試領域扮演了越來越重要的角色，由於製程微縮，記憶體可能會因為製程中的瑕疵，使晶片效能受到影響造成延遲。我們採用了一套新的動態記憶體延遲錯誤模型，這套延遲錯誤模型，是由時間參數的觀念而來。只要在測試過程中採用全速時脈，利用錯誤模型定義的測試方式，可測得記憶體晶片可能發生的延遲錯誤。我們將這套延遲錯誤的定義方式加入了RAMSES，修改並重新命名為RAMSES-D，除了支援傳統的記憶體功能錯誤之外，另外能夠支援新的延遲錯誤。最後，我們提出了權重耦合錯誤的觀念。耦合錯誤的個數本身不能夠準確的代表錯誤發生的真正情況，因為晶片的錯誤是由晶片各層之間不正確的開路、短路造成。然而傳統上耦合錯誤的個數卻涵蓋了整個晶片的面積，很多不可能發生的耦合錯誤也被涵蓋計算，這是不合理的情況。我們提出了一套權重方程式，針對每一個耦合錯誤進行加權計算，我們改變了記憶體的組成方式，針對耦合錯誤加權計算後的結果進行比較。
實驗結果顯示，我們利用錯誤模擬器進行最佳化之後得到的測試樣本，相較於原本提出的測試樣本減少了23.3%的測試樣本長度。在權重耦合錯誤方面，我們發現傳統的錯誤個數計算方式，低估了字元間偶合錯誤的錯誤涵蓋率；而權重方程式，能夠將耦合錯誤的計算方式修改成較為合理的情況。

Memory fault simulator is an important tool for memory test sequence optimization. Traditional sequential fault simulation algorithm has time complexity O(N3) (N: number of cells in memory), which may be too slow to simulate a large number of memory words. Therefore, we had developed a fault simulator called Random Access Memory Simulator for Error Screening (RAMSES). RAMSES uses fault descriptors to describe fault models' behaviors, which can reduce the time complexity to O(N2) and support new fault models.
Delay fault plays a more and more important role in memory testing. In this thesis, we adopt new delay fault models targeting DRAM timing parameters and modify RAMSES that is now called RAMSES-D. Finally, the concept of weighted coupling fault is proposed. Fault count itself cannot accurately represent the real coupling fault distribution. Even if the same fault model is concerned, cells in diRerent positions will have diRerent fault occurrence probability. We propose a weight function and assign a weight to each coupling fault, and modify the fault coverage calculation method. The weighted fault coverage shows the effectiveness of the weight function, and that different coupling fault ratio varies with
diRerent memory configuraitons.
We propose a 23N March test pattern for delay fault models, which reduces 23.3% test length from originally proposed delay fault test patterns. With the weight function, we can use physical information to calculate coupling fault coverage. Experimental result shows that the weight of intra-word coupling fault can be 10% to 14%; while the original fault count method cannot distinguish the degree of importance between diRerent memory configurations.

Introduction 1
1 Motivation . . . . . . . . . . . . . . . . . . . . . . 1
2 PreviousWorks  . . . . . . . . . . . . . . . . . . . . 3
3 ProposedMethod . . . . . . . . . . . . . . . . . . . . 4
4 Organization . . . . . . . . . . . . . . . . . . . . . 5
Memory Fault Simulation 6
1 Fault Descriptors . . . . . . . . . . . . . . . . . .  6
2 Fault Simulation Report . . . . . . . . . . . . . . .  8
SDRAM Delay Fault Simulation 11
1 DRAM Architecture . . . . . . . . . . . . . . . . . . 11
1.1 SDRAM Commands and Timing Parameters . . . . . . . .13
2 SDRAMDelay FaultModels . . . . . . . . . . . . . . . .14
2.1 Sub-BL Delay Fault (SBDF) . . . . . . . . . . . . . 16
2.2 Main-BL Delay Fault (MBDF) . . . . . . . . . . . . .17
2.3 Read Driver Delay Fault (RDDF) . . . . . . . . . . .17
3 Modifications for Delay Faults in RAMSES . . . . . . .17
3.1 User's Spec . . . . . . . . . . . . . . . . . . . . 18
3.2 SimulatedMemory Structure . . . . . . . . . . . . . 20
3.3 Delay Fault Number Calculation . . . . . . . . . . .23
SDRAM Weighted Coupling Fault Simulation 24
1 Concept ofWeighted Coupling Fault . . . . . . . . . . 24
2 Modifications for Weighted Coupling Fault . . . . . . 30
2.1 Weight Function . . . . . . . . . . . . . . . . . . 30
Experimental Results 33
1 Delay Fault Simulation . . . . . . . . .  . . . . . . 33
2 Weighted Coupling Fault Simulation . . . . . . . . .  36
2.1 Block Configuration . . . . . . . . . . . . .  . .  37
2.2 Number of Data Bits per Block . . . . . . . . . . . 40
2.3 Data Bit Distribution in Block . . . . . . . . . . .41
Conclusions and Future Work 45
1 Conclusions . . . . . . . . . . . . . . . . . . . . . 45
2 FutureWork . . . . . . . . . . . . . . . . . . . . .  45

                                

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