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研究生： 黃羿豪
Huang, Yi-Hao
論文名稱： 比較器對於類比數位轉換器的影響探討
An investigation of Comparator Impacts on Analog-to-Digital Converters
指導教授： 張彌彰
Chang, Mi-Chang
口試委員: 徐永珍
Hsu, Yung-Jane
盧向成
Lu, Shiang-Cheng
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2020
畢業學年度： 108
語文別： 英文
論文頁數： 82
中文關鍵詞： 比較器 、類比數位轉換器 、亞穩態
外文關鍵詞： comparator, analog-to-digital converter, metastability
相關次數： 點閱：73  下載：0 
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    • 比較器是類比數位轉換器的一個關鍵元件。它比較輸入訊號並且放大差異，然而，當輸入訊號彼此非常接近時，會出現亞穩態。在這種情況下，它需要很長時間才能解決比較結果。 因此，亞穩態區域對比較器的分辨率，速度和功耗具有決定性的影響。 為了克服這個問題，後續的數位電路需要被精心地設計以處理亞穩性問題。 無論是否需要亞穩檢測信號，拓撲結構以及數位電路的尺寸大小都需要被正確地選擇，以最小化其影響。

    本論文著重於分析存在亞穩態的情況下比較器的影響。首先，分析在快閃式類比數位轉換器中的閂鎖設計。第二，分析亞穩態偵測器的設計運作。第三，分析用於異步類比數位轉換器的互斥或閘設計。最後，分析正反器的電容負載對比較器的影響。

    透過這些分析，我們設計了一個十位元每秒五百萬次的取樣頻率的連續漸進式類比數位轉換器。此轉換器以0.35um製程設計且操作電壓為3.3伏特。設計的重心則是在連續漸進式的邏輯設計。在設計過程中，為了能迅速找到亞穩區，並能對其影響做出分析，我們也開發出自動化的演算法。此演算法加快了設計速度並讓使用者能夠解決潛在的問題。

    The comparator is a key element in Analog-to-Digital (A/D) converter. It compares the input signals and amplifies the differences, however, when the input signals are very close to each other, the metastability state can occur. In this case, it can take a very long time to resolve the comparison result. Thus, the metastability region has deterministic impacts on the resolution, speed and power consumption of the comparator. To overcome this problem, the follow-on digital circuits need to be carefully designed to handle the metastability issue. The topology as well as the sizing of the digital circuit need to be properly selected to minimize the impacts, regardless the need of a metastability detection signal.

    This thesis focuses the analysis of the impacts of a comparator in the presence of a metastability state.
    First, it analyzes the design of the latches following the comparator in a flash analog-to-digital converter.
    Second, it analyzes the operation and design of the metastability detector.
    Third, it analyzes the XOR gate used in an asynchronous analog-to-digital converter.
    Finally, it analyzes the impacts of the capacitor loading of the flip-flops on the comparator.

    From these analyses, a 10-bit 5MS/s successive approximation register analog-to-digital converter is demonstrated. It is designed using 0.35um CMOS technology with a supply voltage of 3.3V. Special attention is paid in designing the SAR control logic. To speed up the design and address all potential issues, computer algorithms have been developed and implemented to automate the process. Using these algorithms, we were able to locate the metastability region and analyze it's impacts.

    中文摘要 iii Abstract v Contents vii List of Figures ix List of Tables xiii Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivation 1 1.3 Thesis Organization 2 Chapter 2 Performance and Architectures of A/D Converters 5 2.1 Performance of A/D Converters 5 2.1.1 Static Parameters 5 2.1.2 Dynamic Parameters· 9 2.2 Architectures of A/D Converters· 11 2.2.1 Flash A/D Converter· 12 2.2.2 Pipeline A/D Converter 13 2.2.3 Successive Approximation Register A/D Converter 13 2.2.4 Comparison of popular A/D architectures 16 Chapter 3 Design of Successive Approximation Register A/D Converter 17 3.1 Sample and Hold Circuit· 17 3.1.1 Non­ideal Effect of Switch 18 3.1.2 Design Consideration on Analog Switch Non­ideal Effects 22 3.2 Comparator 27 3.3 Digital­to­Analog Converter 27 3.3.1 Resistor Based Architectures 27 3.3.2 Capacitor Based Architectures 30 3.3.3 Current Source Based Architectures 32 3.4 SAR Control Logic 32 Chapter 4 Comparator with Digital Circuit 35 4.1 Comparator 35 4.1.1 Operation of Comparator 36 4.1.2 Performance Overview 37 4.1.3 Topologies of Comparator 39 4.2 Algorithm of Evaluating Resolution of Comparator on Simulation 40 4.3 Algorithm of Sizing of Logic Gate 41 4.4 Comparator with NAND Latch 44 4.5 Comparator with Metastability Detector, MD 50 4.5.1 Threshold Inverter Quantization, TIQ 51 4.5.2 Performance of Comparator with Metastability Detector 53 4.6 Comparator with XOR· 57 4.7 Comparator with D flip­flops, DFFs 66 Chapter 5 Architecture and Simulation of SAR A/D Converter 75 5.1 Architecture of SAR A/D Converter Based on Comparator Consid­ eration 75 5.2 Simulation of SAR A/D Converter 76 Chapter 6 Conclusions and Future Work 79 6.1 Conclusions 79 6.2 Future Work 80 References 81

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