在半導體製造中，準確的瑕疵分類對於確保產品品質與降低故
障元件釋出風險至關重要。然而，積體電路（IC）佈局的複雜特
性使得瑕疵外觀變異性極大，為分類模型帶來相當困難的挑戰。
我們的研究提出一套針對半導體瑕疵分類所設計的深度學習分類
架構，專門解決瑕疵類別內部差異大與類別極度不平衡的問題。
所提出的損失函數能提升模型區分正常與瑕疵樣本的能力，同時
維持良好的類別間可分辨性。此外，我們設計了適用於實務上的
信心度篩選機制，針對正常與瑕疵圖像設置不同的信心門檻，有
效降低人工檢查的負擔，並提升整體決策的可靠性。在來自聯電
（UMC）的工業級資料集上進行實驗，結果顯示本方法在準確辨識
瑕疵樣本方面達到最優秀的表現，特別是在降低誤將瑕疵判斷為
正常影像的情況上成效顯著。本研究成果為半導體製造場域提供
一個實用且具可擴展性的瑕疵分類解決方案。

Accurate defect classification is critical in semiconductor manufacturing to ensure product quality and reduce the risks associated with releasing faulty components. However, the intricate nature of integrated
circuit (IC) layouts introduces substantial variability in defect appearance, posing significant challenges for classification models. In this study,
we propose a robust deep learning-based classification framework tailored to address the unique challenges of semiconductor defect inspection, including intra-class diversity and extreme class imbalance. Our
approach incorporates a novel loss function that enhances the model’s
ability to distinguish between normal and defective samples while preserving inter-class separability. Furthermore, we introduce a customized
filtering-out mechanism that considers the different confidence thresholds required for normal and defect layouts, thereby reducing manual
inspection load and improving overall decision reliability. Experimental results on the UMC industrial dataset demonstrate that our method
achieves state-of-the-art performance, particularly in minimizing the false
classification of defective images as normal. This advancement offers a
practical and scalable solution for real-world semiconductor defect classification in manufacturing environments.