研究生: |
張家豪 |
---|---|
論文名稱: |
應變矽於奈米結構之分析與設計 Analysis and Design of Nanoscale Strained Silicon |
指導教授: | 江國寧 |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 動力機械工程學系 Department of Power Mechanical Engineering |
論文出版年: | 2004 |
畢業學年度: | 92 |
語文別: | 中文 |
論文頁數: | 80 |
中文關鍵詞: | 奈米 、應變矽 、有限單元法 |
外文關鍵詞: | strained siicon |
相關次數: | 點閱:80 下載:0 |
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應變矽(Strained Silicon)運用於NMOS時,因矽受到張力應變會令其載子遷移率增加,故能夠提升NMOS的運算速度。應變矽的產生方式主要有兩種,可分為矽/矽鍺異質結構與氮化矽應力層。本研究利用有限單元法針對矽/矽鍺異質結構及氮化矽應力層發展數值模擬方法。對矽/矽鍺異質結構而言,主要是運用虛擬的熱膨脹係數之差異量以模擬兩者晶格常數之不匹配所造成之應變。本研究針對單閘極與三閘極之NMOS的奈米結構進行參數化分析,其結果顯示,當結構長度小於50nm時,有可能因為邊緣的彎矩造成整個應變矽均受到壓應變,導致NMOS之效能無法達到有效的提升。
氮化矽應力層之殘留應力包括熱應力與內應力,本研究運用預應力的方式以模擬不同的內應力對結構所造成之影響。吾人施加內應力1GPa於氮化矽薄膜,且給予400K的降溫負載於此NMOS元件,由模擬結果可知,電晶體通道中最大的x方向應變為0.6%,而內應力為主要影響應變量的關鍵。
藉由有限單元法建立應變矽之模擬方式,本研究中矽/矽鍺異質結構的模擬結果與文獻中的實驗結果相近,證明矽/矽鍺異質結構利用有限單元法之模擬方式的可行性。文中亦針對奈米結構進行有限單元參數化分析,以詳細討論各項參數與應變矽之關係。對於奈米結構而言,本研究所建立之模擬方式可詳盡探討彎矩對應變矽之力學行為,並可依此對NMOS元件進行分析與設計。
Mobility and current drive improvements associated with the tensile strained-silicon in NMOS. The tensile strained-silicon is based on the Si/Si1-xGex or “highly-tensile” silicon nitride capping layer. This research provides a numerical simulation of finite element method to solve stress-strain behaviors of the strained-silicon.
The lattice mismatch between Si and Si1-xGex is simulated in the framework of thermoelasticity. Si and Si1-xGex is assigned in different thermal-expansion coefficients such that the misfit across the interface is met. The parametric analysis is studied for the Si/Si1-xGex nano-structure of single and triple gate NMOS. It is worth noting that when the mesa length is less than 50nm, the entire surface of the top Si layer depicts compressive x-directional strain. This result indicates that an extra small Si/SiGe/Si stack mesa may be inactive for increasing the mobility of the NMOS device.
The stress from the silicon nitride capping layer is uniaxially transferred to the NMOS channel through the source-drain region to create tensile strain in NMOS channel. The residual stress of the silicon nitride capping layer includes the intrinsic stress and thermal stress. This study analyzes the distribution of strain in NMOS channel by using “prestress method” proposed in this investigation to simulate the different intrinsic stress. The maximum x-directional strain of NMOS channel is 0.6% when the model is gave 1GP of the intrinsic stress of the silicon nitride capping layer under a temperature loading of -400K.
The simulate result of Si/Si1-xGex is close to the experimental data of the reference. It indicates that applying the numerical simulation of finite element method to solve stress-strain behaviors of the strained-silicon is feasible. This study also gives detailed analysis about the relationship between different strained-silicon dimensions and strain distributions. The parametric studies can provide the design rule for the mechanical behavior of the nanoscale strained-silicon.
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