改進同步器之平均故障間隔時間｜國立清華大學博碩士論文庫

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研究生：	朱晉緯 Chu, Chin-Wei
論文名稱：	改進同步器之平均故障間隔時間 Improving synchronizer’s mean time between failures
指導教授：	張彌彰 Chang, Mi-Chang
口試委員:	馬席彬 Ma, Hsi-Pin 盧向成 Lu, Shiang-Cheng
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2017
畢業學年度：	105
語文別：	英文
論文頁數：	85
中文關鍵詞：	亞穏態、同步器、積體電路、平均故障間隔時間
外文關鍵詞：	intergrated, MTBF
相關次數：	點閱：69 下載：0
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隨著半導體技術的持續演進，單一晶片上能透過放置越來越多個電晶體來實做出更加複雜的功能。這些複雜的功能通常被分割成可能有不同時脈頻率以及供給電壓的子系統來達到更好的效能。然而，如果訊號在數個不同的時脈區域中傳遞，要直接檢查時間限制是不可能的。為了解決可靠度的問題，同步器被用來同步這些訊號，以此來減少傳遞錯誤。
平均故障間隔時間(MTBF)被用來表徵同步器的穩定度，而解析時間常數(τ)對於平均故障間隔時間的改進是個重要的參數，因為越小的解析時間常數能產生越長的平均故障間隔時間。我們開發出一個能由時間窗口方程式推導出的模擬方法來精準地測量解析時間常數，使用這個方法我們可以發現解析時間常數由同步器的第一級所主宰。我們使用HSPICE配合TSMC 65LP的製程來模擬不同的同步器，且找出他們的解析時間常數對於各項效應(溫度、供給電壓、製程變異、混合門檻電壓製程)的敏感度。除此之外，我們也使用兩個被稱為MPDP和MPDAP的優值來比較不同的同步器的整體效能。最後但同樣重要的是，使用這些我們獲得的知識，已經改良出相比於其他已知研究結果少了一半的解析時間常數。

As the semiconductor technology continues to evolve, more and more transistors can be placed on a single chip with more complex functions implemented. These complex functions are usually divided into sub-systems with possibly different clock frequencies and power supplies to achieve better performance. However it’s impossible to check timing constraints directly if signals are transmitted across different clock domains. To deal with this reliability issues, synchronizers are used to synchronize these cross-domain signals to minimize transmission errors.
Mean-time-between-failures (MTBF) is used to characterize reliability of synchronizers. Resolution time constant (τ) is an important parameter for MTBF improvement because smaller τ results in larger MTBF. We develop a simulation method which can be derived from timing window equation to measure τ accurately. Using this method we can find that it is dominated by the first stage of synchronizer. We use TSMC 65LP technology to simulate various synchronizers and find their sensitivities with repect to temperature, supply voltage, process variation, and mix V_th process with HSPICE. In additional we use two Figures of Merits (FOM) called MPDP and MPDAP to compare overall performance of different synchronizers. Last but not least, using the knowledge gained we have improved τ by more than 50% compared to the known published results.

摘要    i
Abstract    ii
致謝    iii
List of Figures    vii
List of Tables    xi
Chapter 1    INTRODUCTION    1
1 Background    1
2 Motivation    1
3 Thesis Organization    2
Chapter 2 METASTABILITY    3
1 Definition of Metastability    3
2 Metastability Generation    5
2.1 Timing Constraints of D Flip-flop    5
2.2 Metastability Behavior    8
3 Metastable Properties    10
3.1 Timing Window    10
3.2 Mean Time Between Failures    12
4 Related Works    13
4.1 On-chip Metastability Measurement Circuit    14
4.2 Shorting Node and Extended Node Method    15
5 Synchronizer    19
6 Published MTBF Models    23
Chapter 3 SIMULATIONS    25
1 Proposed Simulation Method    25
1.1 Derivation of the Simulation Method    25
1.2 The Non-ideal Rough Region in Simulation Curve    27
1.3 Simulation Settings    29
2 τ Model    32
3 Parameterize τ with the Components in DFF    33
3.1 Transmission Gate    34
3.2 Forward Inverter    35
3.3 Backward Inverter    38
3.4 Dominant Effect    40
4 PVT Analysis    43
4.1 Temperature Effect    43
4.2 Design Corner Effect    45
4.3 Supply Voltage Effect    45
5 Mixed Vth Process    46
Chapter 4 PROPOSED DFF SIMULATIONS    50
1 Effect Analysis    50
2 Different Storage Element Application    55
2.1 Quatro Cell    55
2.2 PDFF with Quatro Cell Simulation    56
3 NP Fighting Improvement    58
Chapter 5 FIGURE OF MERIT ANALYSIS    63
1 FOM of different DFF    63
2 Post-layout Simulations    74
Chapter 6 CONCLUSIONS AND FUTURE WORK    79
1 Conclusions    79
2 Future work    82
REFERENCES    83

                                

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