針對內嵌式處理器之功能性路徑延遲錯誤的自我測試方法

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研究生：	李華翰 Hau-Han Lee
論文名稱：	針對內嵌式處理器之功能性路徑延遲錯誤的自我測試方法 A Self-Testing Methodology of Functional Path Delay Fault Test for Embedded Processor
指導教授：	張慶元 Tsin-Yuan Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2003
畢業學年度：	91
語文別：	英文
論文頁數：	55
中文關鍵詞：	內嵌式處理器、功能性自我測試、路徑延遲錯誤
外文關鍵詞：	Self-Testing, Functional Test, Path Delay Fault Test, Embedded Processor
相關次數：	點閱：108 下載：0
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隨著積體電路製造技術的進步，系統單晶片(System-on-Chip)已成為積體電路設計的趨勢。系統單晶片將各種不同特性，不同型態的電路整合在同一塊晶片上，可以達到高效能，低功率損耗的需求。在這篇論文中，我們提出一個針對系統單晶片中的微處理器(Microprocessor)的管線結構(Pipeline Architecture)，做功能性路徑延遲錯誤自我測試的方法。然而我們針對嵌入式的處理器(Embedded-Processor)合成一個軟體測試程式來錯誤，測試程式由原來處理器的指令集所組成，並且利用指令集形式合成測試程式可以達到即時測試(At-Speed Testing)流程的需求。
測試程式的流程主要分成三個部份。第一部份，利用微處理器管線結構的特性，將設計分成數個管線級(Pipeline Stage)，萃取每個管線級可能的輸入限制(Input Constraint)，這些限制描述著微處理器在執行指令的過程可能的輸入組合。第二部份，將這些輸入限制配合自動樣本產生器(Automatic Test Pattern Generation)產生每一管線級的測試樣本(Test Pattern)。由於所有的輸入組合都經過輸入限制的篩選，這時的輸入都是從微處理器的指令集來組成的，而且需要考慮的錯誤範圍(Fault Space)也會跟著縮小。第三部份，我們考慮管線級中相依訊號的關係以及指令集的組合，將這些測試樣本合成一個可執行的測試程式，這個測試程式可以將每個測試樣本的結果送到資料記憶體上(Data Memory)，我們可以由資料記憶體上的結果判斷微處理器的功能是否正常。整個測試程式的流程可以用來產生路徑延遲錯誤的測試程式。最後，本論文以一個ARM 7 相容微處理器進行測試程式合成的流程驗證。合成的測試程式只需要相當短的執行時間就可以將這個微處理器測試完畢。

The Self-testing of an embedded processor core in a system-on-a-chip (SOC) by using its own instruction sequences has several potential benefits which include natural application of functional vectors at-speed, low DFT overhead, and better power and thermal management during testing. However, synthesizing a software test program for an embedded processor to target manufacturing defect is not a trivial task. It requires both gate-level ATPG and test program synthesis with tight integration. In this thesis, a self-testing methodology of functional path delay fault on embedded processor is proposed. Given the instruction set-architecture, and gate-level netlist, test program can be generated by using test program synthesis with constraints. The experimental results for a pipeline processor indicate that the self-testing methodology is useful with delay test ATPG and customized functional test.

Chapter 1 Introduction                                       1
Chapter 2 Preliminary work                                   3

1  Previous Work ..........................................................................................   3

1.1 DEFUSE………………………………………………………………   4

1.2 VERTIS……………………………………………………………….   7

1.3 Functional test generation using commercial ATPG………………….   9

2  Open Problems  .......................................................................................  11

Chapter 3 Embedded Processor Testing Problem                  13

1 Embedded Processor Difficulty and Limitation ……………………………  13

2 Functional Test ..............................................................................................  15

3 Functional Delay Fault Self-Test on Pipeline Processor……………………  17

3.1 Functional Self-Testing on Delay Testing……………………………...  17

3.2 Delay Fault Testing on Embedded Pipeline Processor…………………  18

Chapter 4 Proposed Functional Test Program Synthesis Methodology         21

1 Design Issues of Functional Test Program Synthesis.....................................  21

2 Functional Test Program Synthesis Flow…………………. .........................  23

3 Constraint Extraction………………………..................................................  25

4 Functional Test Program Synthesis……………………................................  29

4.1 Preload Value and Map Address……………………………….…….  31

4.2 Arrange Instruction in Order………………………………………...  34

4.3 Apply Center Instruction…………………………………………….  37

4.4 Resolve Unknown Condition …………………………………….   40

4.5 Propagate Response to Memory…………………………………..   41

5 The difference of stuck-at fault test program and path delay fault test program.......................................................................................................  42

Chapter 5 Experiment Results and Comparisons                 44

Chapter 6 Conclusions and Future Works                         54

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