隨著半導體元件尺寸的持續微縮，關鍵製程需要更先進的微影解決方法，特別是在第一金屬層，其極具挑戰性的線寬間距（18 奈米）以及對極小的線端對線端（Tip-to-Tip, T2T）間距控制，已成為主要難題。本研究全面比較了低數值孔徑（low-NA）的多重曝光技術，特別是自對準雙重曝光（SADP）與自對準曝光-蝕刻-曝光-蝕刻（SALELE），以及新興的高數值孔徑（high-NA）極紫外光（EUV）單次曝光技術於此關鍵應用的表現。

為了解決固有的微影曝光難度，本研究透過嚴謹的模擬探討了特定的優化策略，包括系統性的製程優化以擴大線寬容許度，並比較亮場與暗場光罩對製程視窗與成像品質的影響。研究中系統性地評估了景深（DOF）、標準化影像對比度斜率（NILS）與邊緣位置誤差（CDU / LWR）等關鍵微影指標，以衡量這些策略的有效性。研究結果表明，雖然 SADP 與 SALELE 在結合優化後的多重切割與自對準製程後，能夠在足夠的製程窗口（Process window）下實現小於 20奈米的線寬間距，但同時也增加了製程複雜度、光罩數量及疊對誤差的敏感度。相對地，高數值孔徑微影單次曝光提供了顯著簡化的流程，並可能具備更優越的疊對控制能力；然而，在最緊密的線寬間距下，也面臨著自身的 T2T 解析度極限，因此需要謹慎的光源-光罩共同優化。本研究系統性地分析了不同曝光方案的權衡取捨，並評估了優化方法與應對挑戰策略的成效。研究結果為第一金屬層製程在可製造性與圖形傳真度之間取得平衡，提供了實用的指導方針，為未來半導體節點的圖形化方案選擇與穩健製程開發奠定了寶貴的基礎。

The continuous scaling of semiconductor devices demands advanced lithographic solutions for patterning critical layers, particularly the first interconnect metal, where achieving aggressive pitches (18 nm) and controlling line-end (Tip-to-Tip, T2T) spacing present major challenges. This study provides a comprehensive comparison of low numerical aperture (NA) multiple patterning methods: specifically self-aligned double patterning (SADP), self-aligned litho-etch-litho-etch (SALELE) and emerging high NA EUV single patterning for this critical application. To address inherent patterning difficulties, this research investigates specific optimization strategies through rigorous simulation. Key approaches include systematic application and process optimizations to expand design margins, and a comparative analysis of bright-field versus dark-field mask strategies to enhance process window and image quality. Critical lithographic factors such as Depth of Focus (DOF), Normalized Image Log-Slope (NILS) and Critical Dimension Uniformity(CDU)/Line Width Roughness(LWR) are systematically evaluated as metrics for the efficacy of these strategies. Our findings indicate that while SADP and SALELE can achieve sub-20 nm pitches with robust process windows when coupled with optimized multi-cut and self-aligned process, they inherently increase process complexity, mask count, and overlay sensitivity. Conversely, high-NA EUV single patterning offers a significantly simplified flow and overlay control. However, it faces its own T2T resolution limits at the tightest pitches, necessitating careful source-mask co-optimization. By systematically analyzing these trade-offs and the effectiveness of the proposed optimization and challenge mitigation strategies, this research develops practical guidelines to optimize process for
the first metal interconnect layer. These insights provide a valuable foundation for navigating patterning choices and advancing robust process development for future semiconductor nodes.