摘要
快閃記憶體在目前被廣泛的應用在各項電子產品中，其易於存取、低功率及非揮發性等特質了大多數產品的需求，但其製程複雜，元件微縮不易。因此在操作的模式上，多重邏輯是一個可以考慮的方向。

在快閃記憶體中的寫入機制，通道熱電子寫入的優點是寫入後臨限電壓（Vth）分佈收斂及臨限電壓和閘極電壓(Vg)成正比。我們利用這二個特性建立多重邏輯。在多重邏輯抹除，由於FN抹除收斂性質並不佳，故造成最低態位元分散，這對建立多重邏輯是不利的。本篇論文嘗試利用二階段抹除(2 Step Erase)加以改進，達到每一個臨限電壓分佈區收斂，以達到充分利用工作區（Working Window）並得到最佳的State和State相隔距離。同時二階段抹除在耐力（Endurance）測試中也充分表現其優點。在多重邏輯的操作中，所遇到最大問題是位元線干擾（Bit line disturb or Drain disturb），其次為字元線干擾（Word line disturb or Gate disturb），本篇論文也提出新的寫入方式改善位元線干擾。同時也對新的寫入方式的可靠度分析和傳統通道熱電子寫入作比較。

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