隨著超大規模積體電路技術的不斷進步，為了應對實體設計日益複雜的挑戰，對創新優化技術的需求日益增加。許多相關任務，如超圖分割、圖分割及擺置，皆可被建模為大規模的組合最佳化問題。本博士論文提出多種方法，結合圖神經網路與大型語言模型，以因應不同組合最佳化問題的挑戰。

我們提出了 GenPart 及其延伸版本 GenPart 2.0，這兩者是基於圖神經網路框架所設計的超圖分割器。GenPart 採用了變分嵌入與 V-cycle 優化，在使用單位節點權重的 ISPD98 測資且考量 2% 及 10% 平衡因子下，相較於 hMETIS， 減少平均切割值達 3.32% 與 4.79%。 GenPart 2.0 進一步擴充該方法以支援有不同節點權重的超圖。在使用非單位節點權重的 ISPD98 測資且考量 10% 平衡因子下，GenPart 2.0 相較於 hMETIS 減少了16.11%的平均切割值，突顯了其對實際設計場景的適應能力。

針對圖分割，我們提出了一個多層級圖分割器 GPart，其利用圖神經網路生成的嵌入來優化分割品質。透過使用團擴展將超圖轉換為圖，GPart 可擴展其應用範圍至超圖分割任務。對 Titan23 與 DIMACS 測資（包含多達 1,600 萬個頂點與 5,000 萬條邊）的評估結果顯示，GPart 相較於 METIS 最高可達平均 42.92% 的切割值減少，同時其記憶體使用量比 GenPart 少 12.4 倍。

在 VLSI 擺置領域，我們提出了 HyperPlace，這是一個基於LLM的新型框架，用於優化 GPU 加速擺置工具的超參數。透過使用零樣本學習與少樣本學習，HyperPlace 自動化了超參數調優流程，在 ISPD2005 測資上，相較於 DREAMPlace 2.0，最多降低 1.66% 的半周長線長。此框架展現出與近期的 GPU 加速擺置工具（如 DREAMPlace 2.0 與 Xplace 2.0）的相容性。

本博士論文探索圖神經網路與大語言模型來應對 VLSI 任務中的可擴展性、效率及適應性相關的挑戰。專注於圖及超圖分割與擺置問題，論文所提出的方法有助於推動自動化設計流程的發展，為 VLSI 設計帶來潛在的進展。

The continuous advancements in Very Large Scale Integration (VLSI) technology demand innovative optimization techniques to address the increasing complexity of physical design. Many of these tasks, such as hypergraph partitioning, graph partitioning, and placement, can be formulated as large-scale combinatorial optimization (CO) problems. This dissertation presents multiple methodologies leveraging Graph Neural Networks (GNNs) and Large Language Models (LLMs) to address various CO challenges.

We introduce GenPart and its extension, GenPart 2.0, GNN-based frameworks designed for hypergraph partitioning. GenPart employs variational embeddings and a V-cycle refinement process, achieving 3.32% and 4.79% average cut size reductions over hMETIS on the ISPD98 benchmarks for unit vertex weights, under 2% and 10% balance factors, respectively. GenPart 2.0 further extends the approach to support hypergraphs with varying vertex weights. On the ISPD98 benchmarks, it demonstrated an average cut size reduction of 16.11% compared to hMETIS under a 10% balance factor, highlighting its adaptability to realistic and complex design scenarios.

For graph partitioning, we propose GPart, a multilevel partitioner that uses GNN-generated embeddings to optimize partitioning quality. By converting hypergraphs to graphs via clique expansion, GPart extends its applicability to diverse partitioning tasks, including hypergraph partitioning. Evaluations on Titan23 and DIMACS benchmarks, with graphs containing up to 16 million vertices and 50 million edges, reveal that GPart achieves average cut size reductions of up to 42.92% compared to METIS, while using 12.4$\times$ less memory than GenPart.

In VLSI placement, we introduce HyperPlace, a novel LLM-based framework for hyperparameter optimization in GPU-accelerated placement tools. By leveraging zero-shot and few-shot learning, HyperPlace automates the hyperparameter tuning process, achieving consistent reductions in Half-Perimeter Wire Length (HPWL) of up to 1.66% compared to DREAMPlace 2.0 across the ISPD2005 benchmarks. This framework demonstrates compatibility with modern placement tools, such as DREAMPlace 2.0 and Xplace 2.0.

This dissertation explores GNNs and LLMs to address challenges related to scalability, efficiency, and adaptability in VLSI tasks. By focusing on partitioning and placement problems, the methodologies contribute to the development of automated and intelligent design workflows, offering potential advancements for next-generation VLSI design.