現代的亂序執行 RISC-V 處理器具備複雜的運作機制，使得微架構層級的效能分析變得相當具挑戰性。儘管效能監控單元（PMU）的數量不斷增加，解讀其資料仍需仰賴深入的架構知識。本文提出一種階層式微架構分析（Top-down Microarchitecture Analysis, TMA）的近似方法，用於自上而下分析 RISC-V 處理器上的應用效能。TMA 將效能瓶頸分為四大類，並透過預先定義的公式與 PMU 事件計算各類瓶頸的比例指標。我們展示了此方法在 SiFive RISC-V 處理器上分析 SPEC CPU2006 基準測試的結果。此工作為在 RISC-V 處理器上應用 TMA 第一層分析的初步嘗試。本研究的三項主要貢獻為：(1) 設計並實作適用於 RISC-V 處理器的 TMA 方法，並定義清晰的效能指標；(2) 提出測試案例與驗證方法，用以確認 TMA 指標與 PMU 的正確性；(3) 協助軟體開發者在無需深入微架構知識的情況下進行效能剖析。

Modern Out-of-Order RISC-V CPUs have complex mechanisms, making micro-architecture-level performance analysis challenging. Despite increasing Performance Monitoring Units (PMUs), interpreting this data requires deep architectural knowledge. This work introduces a Top-down Microarchitecture Analysis (TMA) approximation to analyze application performance on RISC-V CPUs. TMA classifies performance issues into four categories by calculating metrics that reflect their proportions using predefined formulas and PMU events. We present the results of applying this method to analyze SPEC CPU2006 benchmarks on a SiFive RISC-V processor. This work is an initial step in analyzing RISC-V CPUs using TMA Level 1. The contributions of this research are threefold: (1) designing and implementing TMA for a RISC-V CPU with clear metric definitions; (2) proposing test cases and methods to verify TMA metrics and PMU implementation; (3) enabling software developers to profile workloads without requiring extensive microarchitecture knowledge.