現今超大型積體電路設計之流程中，關於熱度問題越顯重要。在晶片中，若是熱度無法平均分配於晶片表面的話，將會影響到電路的可靠度，甚至成為晶片效能的瓶頸。
由先前的研究可以發現，把標準單元(standard cell)擺放於適當位置將有助於達到預期的功率消耗。一旦決定了所有標準單元的功率消耗，即可計算出對應的溫度。因此若能在晶片擺放階段中考慮熱度問題是一個重要的課題。
我們將在標準單元的全域擺放階段中考慮其熱度問題，目標要讓整個晶片的溫度分配差異越細微越佳。爲了達到這個目的，我們採用簡化基底溫度模型(compact substrate thermal model)以計算出對應的溫度資訊。另外，我們提出一個修正力導向的方法得出每個標準單元的粗略位置。在我們的修正力導向的方法中，我們轉化已得到的溫度資訊成一組作用於每個標準單元的額外作用力。這個額外作用力可以幫助我們逐漸修正每個標準單元的擺放位置，直到收斂為止。不同於傳統的力導向方法，我們提出一個簡化轉變矩陣(simplified transform matrix)，以求出所需的額外作用力。最後再以後處理技巧求出更好的結果即是讓晶片表面的溫度更能平均分配。由實驗結果可以觀察出，我們的方法(包含修正力導向方法與後處理技巧)可以使原本不考慮熱度問題的擺放結果之熱分配差異改善最多至66.7%。而全部的接線長度(wirelength)比原本不考慮熱度問題的擺放結果之接線長度至多不超過8.81%。

In modern VLSI designs, the thermal problem is more and more important. Unsmooth distributed temperature will affect upon the reliability of circuits and become the performance bottleneck.
Placing cells on appropriate positions can help to obtain desired power dissipation. Once the desired power dissipation is determined, it can be used to calculate the corresponding temperature. As a result, the thermal problem is an important issue that needs to be considered in the placement stage.
In this thesis, we study the problem of global placement for standard cells such that the maximum thermal gradient over a chip is minimized. To achieve this objective, we adopt the compact substrate thermal model to compute the thermal profile, and the force-directed method to determine the rough locations of cells. We use the thermal profile to form the additional force, and refine the locations of cells repeatedly until convergence. Different from pervious works, we adopt a simplified transform matrix to get the target additional force. At last, a post processing technique is used to get an even better thermal placement result. Experimental results show that as compared to a given placement without thermal consideration, the thermal gradient can be improved up to 66.7% after running our force-directed approach and post-processing technique, while the wirelength increase is up to 8.81%.

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