平方計算是乘法運算中的一個特例，傳統上計算平方運算時，可使用乘法器輸入相同的二筆資料執行，以節省成本或由平方器來執行。在數位訊號處理(Digital Signal Processing，DSP)中，平方器電路構成了DSP操作的心臟，例如圖像壓縮、解碼、解調、自適應濾波，最小平均平方等。當高速處理的需求增加和應用程式的進化，實施專用的平方器與平方函數便被特別重視的提出。
最初，平方器採用查表的方法，如果延遲時間是首要考量，則必需與面積的限制在權衡中取得平衡。該方法的主要缺點是造成面積的上升，當輸入的位元數增加時面積會成指數倍的增加。由於現今的成本與線路延遲考量，上述方法已不是最優先採用的方式。為此，大量的研究已經開發了許多不同的方法來實現平方器，改善更加重視的延遲和減少面積的限制。
本論文研究運用K氏乘法器改良傳統平方器，加入可測試設計，以交替邏輯檢測錯誤的存在，應用於50%利用率及100%單一永駐錯誤涵蓋率，所付代價為面積增加 (n^2+454n-264)/(56n^2-96n+40)×100%，延遲時間增加 (n+2)/(4n-4)×100%，其中n為輸入位元數，以n=64為例，增加面積14.73%，延遲時間26.19% ; 所提K氏平方器演算法，在64位元平方器可節省10.65%面積(電晶體數目)。

Squaring is a special case of multiplication. Traditionally, squaring can be performed by using multiplier itself with the same inputs for saving area or a squarer. Squaring circuit forms the heart of different DSP operations such as Image Compression, Decoding, Demodulation, Adaptive Filtering, Least Mean Squaring etc. As the applications evolved and the demand for the high speed processing increased, squaring function and dedicated squarers are implemented.
Initially, squaring is performed by using Look Up Table (LUT) approach if delay is primary concern with the penalty of area. Major drawback of this LUT scheme is large area, which increases exponentially as the number of input bits increases. Due to the cost and the interconnect delay, this approach is not the most preferred implementation. A lot of researches have been conducted in order to develop different methodologies to implement squarer, giving more importance to improve delay and to reduce area constraints.
This research modifies Karatsuba squarer for using an improved algorithm and alternative logic testing. The proposed testable Karstsuba squarer can be applied in the circuit under 50% utilization rate and 100% fault coverage of single stuck-at fault model with the penalties of area increased (n^2+454n-264)/(56n^2-96n+40)×100% and delay (n+2)/(4n-4)×100%. Take n=64 for instance, the area and delay increase 14.73% and 26.19%, respectively. The proposed algorithm can reduce Area of (9n+50)/(92n-14 )×100%(transistor count). For example, the area saved is 10.65% for n=64.

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