浮動式閘極快閃記憶體由於許多問題(如耦合效應及SILC所引起的漏電)而無法滿足元件微縮發展的趨勢，因此利用電荷陷阱式快閃記憶體取代浮動式閘極結構元件是未來發展的趨勢。然而傳統SONOS元件以氮化矽作為儲存層的結構，在發展到次微米以下就無法再以降低穿隧氧化層厚度來提升元件的操作效率，因此便引進了高介電材料來取代傳統ONO結構以提升元件操作效能，但此時面臨到的將是抹除速度與電荷保持力之間的trade-off問題。
本實驗將利用不同高介電係數的材料與氮化矽搭配，以堆疊的方式堆疊出電荷儲存層。研究主要是利用不同材料具有不同的特性，配合堆疊的結構，藉著電荷陷阱密度的多寡、能階大小的改變、K值影響分壓的不同、陷阱能階等種種特性，配合能帶工程堆疊出最佳特性的電荷儲存層。本論文研究的方向主要分為下列三項:
1.探討高介電材料與氮化矽的搭配三明治結構堆疊來做電荷儲存層，將其應用在電荷陷阱式快閃記憶體，討論其對元件特性研究。
2. 討論Si3N4/SiO2/ HfxAlyO結構電荷儲存層應用於電荷陷阱式快閃記憶體，對元件特性的影響。由第一項討論可發現NAN結構可有效同時改善P/E速度及電荷保持力，如何更近一步提升保持力，是本項實驗所要做的。
3. 將各種能帶工程應用於電荷儲存層的電荷陷阱式快閃記憶體元件特性的影響。本章以氮化矽與高介電的材料來堆疊出雙層結構、三明治結構以及階梯式能階結構的快閃記憶體電容元件，對其特性做一研究。
由實驗結果可發現，引進能帶工程，若是利用能隙大小的不同，堆疊出適當結構，將有助於在不犧牲抹除速度下提升電荷保持力。

1.Improvement of P/E speed for NAN structure trapping layer
higher charge tunneling efficiency
lower Ig

2.Trapped charge detrap easier for HfO2 compared with
Si3N4,but that’s a trade-off : erasing speed □ retention

3.Improvement of endurance characteristics for NAN
structure compared with single Si3N4 trapping layer
barrier oxide(Al2O3) reduces the trap generation during
cycling

4.Simultaneous improvement in P/E speed and retention for
Si3N4/Al2O3/HfO2 structure

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