參考電路至今已被研究多年，隨著可攜式電子產品蓬勃發展，低電壓與小面積的積體電路成了目前研究重心。一般參考電路係利用BJT設計以得到穩定的溫度補償輸出。但為了達到更小面積與較低供應電壓，近年來已有不少文獻探討MOS參考電路。然而不管使用BJT或MOS，在考慮功率消耗或運算放大器負載寄生電容及抵補電壓效應下，並聯在它們旁邊的電阻會佔整個晶片面積相當大比例。除此之外，來自供應電壓的雜訊沒辦法完全被排斥，且在高頻應用下，可能耦合至電路衰減輸出訊號。
本研究主要針對上述問題，提出一個新穎的CMOS電壓參考電路，它採用電流鏡作為溫度補償，並且避免使用大電阻以減少晶片面積。設計電路已使用台積電標準0.18 μm CMOS製程實現，後模擬結果在溫度範圍-40 ~ 100 ℃與供應電壓從1.2 ~ 1.98 V變化下，溫度係數變動範圍59.5 ~ 63.8 ppm/℃。在供應電壓1.2 V且頻率10 kHz時，供應電壓與雜訊排斥比為-70 dB。總括來說，本論文採用電流鏡得到低溫度飄移參考電壓，間接避免使用大電阻帶來設計上問題，且供應電壓與雜訊排斥比也有不錯表現。

Reference circuits have been studying for many years. Following the vigorous development of portable electronic products, integrated circuits with low voltage and small area have become the core part of the recent research. Parasitic vertical bipolar junction transistors are commonly used in CMOS voltage reference circuits for a better stability. Recently, MOS reference circuits have been used to replace BJT ones in order to reduce the chip area and supply voltage. Whether BJT or MOS is utilized, the problem that resistances parallelizing on either side of BJT or MOS generally occupy quite large ratio of chip area under the consideration of power consumption and loading parasitic capacitances of op-amp still exists. Another problem worthy of our concern is that spurious signals coming from the supply voltage cannot be adequately rejected and may couple into the circuit to degrade output signal in high frequency applications.
This thesis aims to improve the above problems and proposes a novel voltage reference circuit. A current mirror is designed for temperature compensation and large resistors are defeasible for reduction chip area. Besides, it has been implemented by a 0.18 μm CMOS process with a chip area of 0.023 mm2. Simulation shows that the variation of temperature coefficient is from 59.5 to 63.8 ppm/℃ under the temperature range from -40 to 100 ℃ and a supply voltage variation from 1.2 to 1.98 V. The power noise rejection ratio is -70 dB at 10 kHz with 1.2V supply voltage. In summary, the thesis adopts a current mirror to achieve low-temperature-drift reference voltage and abandons large resistances on design consideration. With this approach, power noise rejection ration is reduced.

[1] M. Sodagar and K. Najafi, “A multi-output supply-independent voltage reference in standard CMOS process for telemetry-powering applications,” International Symposium on Signals, Circuits and Systems, vol. 2, pp. 493-496, July 2003.
[2] J. Doyle, Y. J. Lee, Yong-Bin Kim, H. Wilsch, and F. Lombardi, “A CMOS subbandgap reference circuit with 1-V power supply voltage,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 252-255, Jan. 2004.
[3] D. Hilbiber, “A new semiconductor voltage standard,” IEEE International Solid-State Circuits Conference, vol. VII, pp.32-33, Feb. 1964.
[4] R. Widlar, “New developments in IC voltage regulators,” IEEE International Solid-State Circuits Conference, vol. XIII, pp. 158-159, Feb. 1970.
[5] K. E. Kuijk, “A precision reference voltage source,” IEEE Journal of Solid-State Circuits, vol. 8, pp. 222-226, June 1973.
[6] D. A. Johns and K. Martin, “Analog integrated circuit design,” 1st ed. New York: Wiley & Sons, 1997.
[7] K. N. Leung, P. K. T. Mok, and C. Y. Leung, “A 2-V 23-μA 5.3-ppm/℃ curvature-compensated CMOS bandgap voltage reference,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 561-564, Mar. 2003.
[8] K. N. Leung and P. K. T. Mok, “A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 526-530, Apr. 2002.
[9] R. Dehghani and S. M. Atarodi, “A new low voltage precision CMOS current reference with no external components,” IEEE Transactions on Circuits and Systems, vol. 50, pp. 928-932, Dec. 2003.
[10] M. Filanovsky and A. Allam, “Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits,” IEEE Transactions on Circuits and Systems, vol. 48, pp. 876-884, Jul. 2001.
[11] K. N. Leung and P. K. T. Mok, “A CMOS voltage reference based on weighted △VGS for CMOS low-dropout linear regulators,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 146-150, Jan. 2003.
[12] Y. Dai, D. T. Comer, D. J. Comer, and C. S. Petrie, “Threshold voltage based CMOS voltage reference,” IEE Proceedings of Circuits, Devices and Systems, vol. 151, pp. 58-62, 5 Feb. 2004.
[13] T. Grotjohn and B. Hoefflinger, “A parametric short-channel MOS transistor model for subthreshold and strong inversion current,” IEEE Journal of Solid-State Circuits, vol. 19, pp. 100-112, Feb. 1984.
[14] M. S. Kim et al., “Optical subthreshold current method for extracting the interface states in MOS systems,” IEEE Trans. Electron Device Letters, vol. 25, no. 2, pp. 101-103, Feb. 2004.
[15] Y. Hu and M. Sawan, “A 900 mV 25 μW high PSRR CMOS voltage reference dedicated to implantable micro-devices,” Proceedings of the 2003 International Symposium on Circuits and Systems, vol. 1, pp. 373-376, 25-28 May 2003.
[16] T. Ytterdal, “CMOS bandgap voltage reference circuit for supply voltages down to 0.6 V,” Electronics Letters, vol. 39, pp. 1427-1428, 2 Oct. 2003.
[17] P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, “Analysis and Design of Analog Integrated Circuits,” 4th ed. New York: Wiley & Sons, 2001.
[18] P. E. Allen and D. R. Holberg, “CMOS Analog Circuit Design,” 2nd ed. New York: Oxford, 2002.
[19] E. Bruun and P. Shah, “Dynamic range of low-voltage cascode current mirrors,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 1328-1331, 28 April-3 May 1995.
[20] E. Sackinger and W. Guggenbuhl, “A high-swing, high-impedance MOS cascode circuit,” IEEE Journal of Solid-State Circuits, vol. 25, pp. 289-298, Feb. 1990.
[21] M. Ozbas, D. Patru, and P. R. Mukund, “Power supply noise coupling in a standard voltage reference circuit,” in Proc. IEEE Int. Conf. Systems-on-Chip, pp. 319-322, Sept. 2003.
[22] A. Hastings, “The art of analog layout,” 2nd ed. New Jersey: Prentice-Hall, 2001.
[23] U. Gatti, F. Maloberti and V. Liberali, “Full stacked layout of analogue cells,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 1123-1126, May 1989.
[24] E. Malavasi, D. Pandini and V. Liberali, “Optimum stacked layout for analog CMOS ICs,” in Proc. IEEE Int. Conf. Custom Integrated Circuits, pp. 17.1.1-17.1.4, May 1993.
[25] J. Bruce, H. Li and M. Dallabetta, “An analog layout assistant for matched and balanced CMOS components,” Proceedings of the Eighth Annual IEEE International ASIC Conference and Exhibit, pp. 267-270, Sept. 1995.
[26] K. W. Cheng, “A 1.0-V, 10-Bit CMOS Pipelined Analog-to-Digital Converter,” M.S. thesis, National Taiwan University, Jun. 2002.