隨著科技日益發展與進步，人們的生活愈趨科技化。在顯示科技方面，開始追求高畫面品質的產品。為了有效的提升顯示畫面品質，必須使用高解析度的顯示器驅動晶片驅動高畫質顯示器。然而，隨著解析度的提升，液晶顯示器中的源極驅動器之數位類比轉換器必須操作在更高的資料轉換速率以保持相同的畫面更新率。對於顯示器驅動器的研發成本方面，源極驅動器中的數位類比轉換器的解析度提高，也使得晶片面積增加，製作成本也伴隨著提高。因此本論文研究著重於降低液晶顯示器驅動器的晶片面積，也就是降低晶片製作成本，且能達到相同的驅動效能。
本論文提出一個可應用於液晶顯示器源極驅動器之10位元具有源極追隨器為電壓緩衝器之兩級式數位類比轉換器。所提出之8位元數位類比轉換器在佈局面積與傳統上8位元數位類比轉換器面積比較，以驗證面積大小，結果顯示本論文提出之DAC面積只有傳統上8位元DAC面積之61%。利用0.18-um/0.35-um CMOS製程下線，並量測驗證本論文提出之DAC晶片，量測結果最差DNL與INL分別為0.61 LSB與0.78 LSB。

With the development and progress of technology, people’s lives have been more and more technical. In display technology, making high-definition-screened products becomes the goal. In order to effectively improve the quality of the display device, it is necessary to use high-resolution display driver ICs to drive high-definition displays. However, with improved resolution, digital-to-analog converter (DAC) in the LCD source driver must be operated at a higher data conversion rate to maintain the same frame refresh rate. As for the development costs of display drivers, production costs increase because the chip area becomes bigger, which is caused by the increasing resolution of the digital-to-analog converter (DAC). Therefore, the purpose of this essay focuses on reducing the chip area of liquid crystal displays, that is, reducing chip costs, and achieving the same driving performance.
This thesis propose a 10-bit two-stage DAC with a source follower and a op-amp for LCD source driver ICs. This design requires an 8-bit conventional DAC compared with proposed DAC, enabling a smaller die area. The proposed DAC occupies only 61% of area needed for an 8-bit conventional DAC. The 10-bit prototypes were produced with 0.18-um/0.35-um CMOS technology with the worst DNL/INL being 0.61/0.78 LSB.

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