簡易檢索 / 詳目顯示

研究生: 張家豪
論文名稱: 應變矽於奈米結構之分析與設計
Analysis and Design of Nanoscale Strained Silicon
指導教授: 江國寧
口試委員:
學位類別: 碩士
Master
系所名稱: 工學院 - 動力機械工程學系
Department of Power Mechanical Engineering
論文出版年: 2004
畢業學年度: 92
語文別: 中文
論文頁數: 80
中文關鍵詞: 奈米應變矽有限單元法
外文關鍵詞: strained siicon
相關次數: 點閱:81下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 應變矽(Strained Silicon)運用於NMOS時,因矽受到張力應變會令其載子遷移率增加,故能夠提升NMOS的運算速度。應變矽的產生方式主要有兩種,可分為矽/矽鍺異質結構與氮化矽應力層。本研究利用有限單元法針對矽/矽鍺異質結構及氮化矽應力層發展數值模擬方法。對矽/矽鍺異質結構而言,主要是運用虛擬的熱膨脹係數之差異量以模擬兩者晶格常數之不匹配所造成之應變。本研究針對單閘極與三閘極之NMOS的奈米結構進行參數化分析,其結果顯示,當結構長度小於50nm時,有可能因為邊緣的彎矩造成整個應變矽均受到壓應變,導致NMOS之效能無法達到有效的提升。
    氮化矽應力層之殘留應力包括熱應力與內應力,本研究運用預應力的方式以模擬不同的內應力對結構所造成之影響。吾人施加內應力1GPa於氮化矽薄膜,且給予400K的降溫負載於此NMOS元件,由模擬結果可知,電晶體通道中最大的x方向應變為0.6%,而內應力為主要影響應變量的關鍵。
    藉由有限單元法建立應變矽之模擬方式,本研究中矽/矽鍺異質結構的模擬結果與文獻中的實驗結果相近,證明矽/矽鍺異質結構利用有限單元法之模擬方式的可行性。文中亦針對奈米結構進行有限單元參數化分析,以詳細討論各項參數與應變矽之關係。對於奈米結構而言,本研究所建立之模擬方式可詳盡探討彎矩對應變矽之力學行為,並可依此對NMOS元件進行分析與設計。


    Mobility and current drive improvements associated with the tensile strained-silicon in NMOS. The tensile strained-silicon is based on the Si/Si1-xGex or “highly-tensile” silicon nitride capping layer. This research provides a numerical simulation of finite element method to solve stress-strain behaviors of the strained-silicon.
    The lattice mismatch between Si and Si1-xGex is simulated in the framework of thermoelasticity. Si and Si1-xGex is assigned in different thermal-expansion coefficients such that the misfit across the interface is met. The parametric analysis is studied for the Si/Si1-xGex nano-structure of single and triple gate NMOS. It is worth noting that when the mesa length is less than 50nm, the entire surface of the top Si layer depicts compressive x-directional strain. This result indicates that an extra small Si/SiGe/Si stack mesa may be inactive for increasing the mobility of the NMOS device.
    The stress from the silicon nitride capping layer is uniaxially transferred to the NMOS channel through the source-drain region to create tensile strain in NMOS channel. The residual stress of the silicon nitride capping layer includes the intrinsic stress and thermal stress. This study analyzes the distribution of strain in NMOS channel by using “prestress method” proposed in this investigation to simulate the different intrinsic stress. The maximum x-directional strain of NMOS channel is 0.6% when the model is gave 1GP of the intrinsic stress of the silicon nitride capping layer under a temperature loading of -400K.
    The simulate result of Si/Si1-xGex is close to the experimental data of the reference. It indicates that applying the numerical simulation of finite element method to solve stress-strain behaviors of the strained-silicon is feasible. This study also gives detailed analysis about the relationship between different strained-silicon dimensions and strain distributions. The parametric studies can provide the design rule for the mechanical behavior of the nanoscale strained-silicon.

    目錄 Ⅰ 表目錄 Ⅲ 圖目錄 Ⅳ 第一章 導論……………………………………………………………… 1 1.1 研究動機………………………………………………………….. 1 1.2 文獻回顧………………………………………………………….. 2 1.3 研究目標………………………………………………………….. 4 第二章 應變矽結構分析……………………………………………… 6 2.1 張力應變對矽之電子特性的影響………………………………. 6 2.2 金氧半場效電晶體操作原理……………………………………. 7 2.3 應變矽的操作原理………………………………………………. 8 2.3.1 矽鍺異質結構分析…………………………………………. 8 2.3.1.1 矽鍺異質結構的材料特性………………………….. 8 2.3.1.2 矽/矽鍺雙層結構之應變分析………………………. 10 2.3.1.3 使用拉曼光譜圖量測矽鍺異質結構之應變……….. 13 2.3.2 氮化矽應力層………………………………………………. 14 第三章 有限單元分析模型……………………………………………… 18 3.1 矽鍺異質結構…………………………………............................. 18 3.1.1單閘極金氧半電晶體……………………………………….. 18 3.1.1.1 有限單元模型之建立................................................. 18 3.1.1.2 有限單元分析……………………………………….. 18 3.1.2三閘極金氧半電晶體……………………………………….. 21 3.1.2.1 有限單元模型之建立…………………………......... 21 3.1.2.2 有限單元模型分析………………………………….. 21 3.2 氮化矽應力層…………………………………………………….. 22 3.2.1 有限單元模型之建立……………......................................... 22 3.2.2 有限單元分析………………………………………………. 22 第四章 結果分析與討論………………………………………………… 25 4.1 矽鍺異質結構…………………………………………………….. 25 4.1.1 單閘極金氧半電晶體……………………………………....... 25 4.1.1.1 模型之參數化設計…………………………………… 25 4.1.1.2 參數的模擬結果分析………………………………… 25 4.1.1.3 有效應變區域的分析……………………………....... 32 4.1.2 三閘極金氧半電晶體模擬結果討論……………………....... 33 4.2 氮化矽應力層模擬結果討論……………………………………. 34 第五章 結論………………………………………………………………. 37 參考文獻…………………………………………………………………… 39 圖表………………………………………………………………………… 45 表目錄 表一 矽與矽鍺化合物的材料特性…………………………………... 45 表二 矽與矽鍺化合物的單方向熱膨脹係數之設定(升溫) ………… 45 表三 矽與矽鍺化合物的單方向熱膨脹係數之設定(降溫)…………. 45 表四 Si0.8Ge0.2的材料特性之設定(升溫之等方向性熱膨脹係數)...... 46 表五 Si0.8Ge0.2的材料特性之設定(降溫之等方向性熱膨脹係數)...... 46 表六 Si0.8Ge0.2的材料特性之設定(升溫之單方向性熱膨脹係數)...... 46 表七 Si0.8Ge0.2的材料特性之設定(降溫之單方向性熱膨脹係數)...... 46 表八 三閘極電晶體的材料特性之設定(等方向性熱膨脹係數)……. 47 表九 氮化矽薄膜之單閘極電晶體材料特性的設定………………... 47 表十 等比例尺寸的應變比較………………………………………... 47 表十一 結構長度與應變區域的關係…………………………………... 48 圖目錄 圖2-1 未受應變之矽基材的六個傳導帶,(a)三維示意圖,(b)三維投影至平面示意圖…....................................................................... 49 圖2-2 應變矽的二傳導帶和四傳導帶,(a)三維示意圖,(b)三維投影至平面示意圖…..………………………………………………. 49 圖2-3 矽受拉應變後的能量分佈……………………………………... 50 圖2-4 NMOS電晶體的結構………………………………………….. 50 圖2-5 矽鍺磊晶層與矽基材的晶格排列…..…………………………. 51 圖2-6 矽鍺磊晶層成長於矽基材上………………..…………………. 51 圖2-7 矽鍺磊晶層與矽基材間的差排效應……................................... 52 圖2-8 NMOS電晶體的結構圖,紅色箭頭代表電流通過的區域及方向………………………………………………………………... 52 圖2-9 (a)三閘級電晶體的結構(b) 三閘級電晶體的通道中,電流主要在通道與閘極接觸的表面(淺綠色部分)流動,如紅色箭頭所示……………………………………………………………... 53 圖2-10 三閘級電晶體的通道,內部為矽鍺化合物,表面為應變矽… 53 圖2-11 受應變之矽/矽鍺雙層結構的橫切面………………………….. 54 圖2-12 氮化矽應力層中矽與氮原子的個數比與殘留應力之關係…... 54 圖2-13 Intel所發表的覆蓋氮化矽應力層之NMOS電晶體結構……. 55 圖2-14 當氮化矽沉積於矽基板上,不同的薄膜應力對外觀造成之變形………………………………………………...……………… 55 圖2-15 利用高拉伸應力的氮化矽應力層給予NMOS通道拉伸應力.. 56 圖3-1 矽/矽鍺雙層結構……………………………………………….. 56 圖3-2 矽/矽鍺/矽三層結構之方型平台(Mesa)………………………. 57 圖3-3 矽/矽鍺/矽三層結構……………………………………………. 57 圖3-4 矽/矽鍺/矽三層結構的四分之一模型…………………………. 58 圖3-5 三閘極電晶體通道的四分之一模型…………………………... 58 圖3-6 披覆氮化矽薄膜之單閘極電晶體的結構……………………... 59 圖3-7 氮化矽應力層之單閘極電晶體主要邊界條件的設定………... 59 圖3-8-1 預應力的邊界條件設定………………………………………... 60 圖3-8-2 預應力的邊界條件設定(局部放大)……………………………. 60 圖4-1 矽鍺異質結構之參數化…………………………….………….. 61 圖4-2 升溫之不同矽鍺化合物厚度於底層矽厚度參數化之比較(等方向之熱膨脹係數) …………………………………................. 61 圖4-3 降溫之不同矽鍺化合物厚度於底層矽厚度參數化之比較(等方向之熱膨脹係數) ……………………………………………. 62 圖4-4 升溫前與升溫後的變形(等方向之熱膨脹係數) ………............ 62 圖4-5 降溫前與降溫後的變形(等方向之熱膨脹係數) ……………… 63 圖4-6 上層矽之厚度與x方向應變的關係(等方向之熱膨脹係數)…. 63 圖4-7 不同矽鍺化合物厚度於底層矽厚度參數化之比較(水平雙軸方向之熱膨脹係數) ……………………………………………. 64 圖4-8 升溫前與升溫後的變形(水平雙軸方向之熱膨脹係數)….…… 64 圖4-9 降溫前與降溫後的變形(水平雙軸方向之熱膨脹係數)..……... 65 圖4-10 上層矽之厚度與x方向應變的關係(水平雙軸方向之熱膨脹係數)….…………………………………………………………. 65 圖4-11 文獻[9]中的應變矽結構………………………………………... 66 圖4-12 應變矽結構的四分之一模型…………………………………... 66 圖4-13 應變矽結構之x方向應變分佈………………………………… 66 圖4-14 結構長度與x方向應變的關係………………………………… 67 圖4-15 x方向應變分佈圖(結構長度:1,500nm) ……………………….. 67 圖4-16 x方向應變分佈圖(結構長度:500nm) …………………………. 68 圖4-17 矽鍺化合物之厚度與x方向應變的關係……………………… 68 圖4-18 上層矽之厚度為5nm的x方向應變分佈…………………….. 69 圖4-19 上層矽之厚度為50nm的x方向應變分佈……………………. 70 圖4-20 上層矽之厚度為300nm的x方向應變分佈………………….. 70 圖4-21 無因次化之結構尺寸與x方向應變的關係…………………… 71 圖4-22 矽表面位於z=0且沿著x軸的單元之x方向應變................... 71 圖4-23 矽表面位於z=0且沿著x軸的單元之x方向應變………....... 72 圖4-24 有效應變區域之總長度與矽鍺化合物之厚度的關係………... 72 圖4-25 矽表面位於z=0且沿著x軸的單元之x方向應變…………… 73 圖4-26 有效應變區域之總長度與上層矽之厚度的關係……………... 73 圖4-27 結構長度為150nm的z方向應變分佈……………………….. 74 圖4-28 電晶體通道於z=0的z方向應變分佈………………………… 74 圖4-29 結構中間表面z方向之應變與x軸的關係…………………… 75 圖4-30 矽表面位於z=0且沿著x軸的單元之x方向應變…………… 75 圖4-31 z方向應變與矽薄膜的厚度及結構長度的關係………………. 76 圖4-32 氮化矽應力層受到2GPa的預應力…………………………… 76 圖4-33 模擬結構受到內應力(1GPa)時的應力分佈…………………… 77 圖4-34 模擬結構受到內應力(1GPa)時的x方向的應變分佈………… 77 圖4-35 電晶體通道部分受到內應力(1GPa)時的x方向應變分佈………………………………………………………………... 78 圖4-36 電晶體的x方向應變分佈(內應力為1GPa且由400°C降至25°C)……………………………………………………………. 78 圖4-37 電晶體通道部分的x方向應變分佈(內應力為1GPa且由400°C降至25°C)………………………………………………..…. 79 圖4-38 電晶體通道部分的x方向應變分佈(內應力為1GPa且由400°C降至25°C)…………………………..……………………….. 79 圖4-39 電晶體通道部分的x方向應變分佈(內應力為500MPa且由400°C降至25°C)……………………………………………….. 80

    1. Y. H. Xie, Don Monroe, E. A. Fitzgerald, P. J. Silverman, F. A. Thiel, and G. P. Watson, “Very high mobility two-dimensional hole gas in Si/GexSi1-x/Ge structures grown by molecular beam epitaxy.pdf,” Appl. Phys. Lett. 63, pp. 2263-2264 (1993).
    2. T. Mizuno, N. Sugiyama, T. Tezuka, and S. Takagi, “(110) Strained-SOI n-MOSFETs With Higher Electron Mobility,” IEEE Electron Device Lett., Vol. 24, No. 4, pp. 266-268 (2003).
    3. K. Rim, L. J. Huang, ”Silicon Update,” Compound Semiconductor magazine (August 2001)
    4. T. Tezuka, N. Sugiyama, and S. Takagi, “Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction,” Appl. Phys. Lett., 79, pp. 1798-1800 (2001).
    5. T. Tezuka, N. Sugiyama, S. Takagi, and T. Kawakubo, “Dislocation-free formation of relaxed SiGe-on-insulator layers,” Appl. Phys. Lett. 80, pp. 3560-3562 (2002).
    6. J. C. Tsang, P. M. Mooney, F. Dacol, and J. O. Chu, “Measurements of alloy composition and strain in thin GexSi1–x layers, ” Appl. Phys. J., 75, pp. 8098-8108 (1994).
    7. W. M. Chen, P. J. Mcnally, G. D. M. Dilliway, J. Bonar, T. Tuomi, and A. F. W. Willoughby, ”Stress characterization of device layers and the underlying Si1-xGex virtual substrate with high-resolution micro-Raman spectroscopy,” Journal of Materials Science: Materials Electronics, 14, pp. 455-458 (2003).
    8. D. Zubia, S. D. Hersee, and T. Khraishi, ”Strain partitioning in coherent compliant heterostructures,” Appl. Phys. Lett., 80, 740 (2002).
    9. H. Yin, K. D. Hobart, F. J. Kub, S. R. Shieh, T. S. Duffy, and J. C. Sturm, “Strain partition of Si/SiGe and SiO2/SiGe on compliant substrates,” Appl. Phys. Lett. 82, pp. 3853-3855 (2003).
    10. Y. H. Lo, ”New approach to grow pseudomorphic structures over the critical thickness,” Appl. Phys. Lett., 59, pp. 2311-2313 (1994).
    11. P. V. Mieghem, S. C. Jain, J. Nijs, and R. V. Overstraeten, ”Stress relaxation in laterally small strained semiconductor epilayers,” Appl. Phys. J., 75, pp. 666-668 (1994).
    12. S. Chrisiansen, M. Albrecht, H. P. Strunk, and H. J. Maier, ”Strained state of Ge(Si) islands on Si Finite element calculations and comparison to convergent beam electron-diffraction measurements,” Appl. Phys. Lett., 64, pp. 3167-3619 (1994).
    13. T. Benabbas, P. Francois, Y. Androussi, and A. Lefebvre, ”Stress relaxation in highly strained InAs/GaAs structures as studied by finite element analysis and transmission electron microscopy,” Appl. Phys. J., 80, pp. 2763-2767 (1996).
    14. P. L. Novikov, Y. B. Bolkhovityanov, O. P. Pchelyakov, S. I. Romanov, and L. V. Sokolov, ”Specific behaviour of stress relaxation in Gex/Si1-x films grown on porous silicon based mesa substrates computer calculations,” Semicond. Sci. Technol., 18 , pp. 39–44(2003)
    15. L. B. Freund, and W. D. Nix, ”A critical thickness condition for a strained compliant substrate-epitaxial film system,” Appl. Phys. Lett., 69, pp. 173-175 (1996).
    16. H. Yin, R. Huang, K. D. Hobart, Z. Suo, T. S. Kuan, C. K. Inoki, S. R. Shieh, T. S. Duffy, F. J. Kub, andJ. C. Sturm, ”Strain relaxation of SiGe islands on compliant oxide,” Appl. Phys. J., 91, pp. 9716-9722 (2002).
    17. G. Kästner, and U. Gösele, ”Principles of strain relaxation in heteroepitaxial films growing on compliant substrates,” Appl. Phys. J., 88, pp. 4048-4055 (2000).
    18. M. Fatemi, and E. E. Stahlbush, “X-ray rocking curve measurement of composition and strain in Si-Ge buffer layers grown on Si substrates.,” Appl. Phys. Lett., 58, pp. 825-827 (1991).
    19. 賴莉雯,”無應力矽鍺合金層的光學特性”,國立師範大學,(2002)
    20. S. I. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, “Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal-oxide-Semiconductor Field-effect transistors,” Appl. Phys. J., 80, pp. 1567-1577 (1996).
    21. J. C. Tsang, P. M. Mooney, F. Dacol, And J. O. Chu, “Measurement of alloy composition and strain in thin GexSi1-x layers,” Appl. Phys. J., 75, pp. 8098-8108 (1994).
    22. P. D. Moran, D. M. Hansen, R. J. Matyi, L. J. Mawst, andT. F. Kuech, “Experimental test for elastic compliance during growth on glass-bonded compliant substrates,” Appl. Phys. Lett., 76, pp. 2541-2543 (2000).
    23. T. Vogelsang , and K. R. Hofmann, “Electron transport in strained Si layers on Si1-xGex substrates,” Appl. Phys. Lett., 63, pp. 186-188 (1993).
    24. E. Kasper, “Strained silicon germanium heterostructures for device applications,” International Journal of Modern Physics B, Vol. 16, Nos. 28 & 29, pp. 4189-4194 (2002).
    25. M. A. Herman, “Silicon-Based Heterostructures: Strained-Layer Growth by Molecular Beam Epitaxy,” Cryst. Res. Technol., 34, pp. 583-595 (1999).
    26. Y. B. Bolkhovityanov, O. P. Pchelyakov, and S. I. Chikichev, “Silicon-germanium epilayers: physical fundamentals of growing strained and fully relaxed heterostructures,” Physics-Uspekhi, 44, pp. 655-680 (2001).
    27. E. Lea, and B. L. Weiss, “Modeling and characteristics of photoelastic waveguide in Si1-xGex/Si heterstructures,” IEE Proc.-Optoelectron., Vol. 147, No. 2, pp. 123-131 (2000)
    28. K. E. Gonsalves, S.P. Rangarajan, and J. Wang,“Nanostructured materials and nanotechnology,”Academic Press, (2002).
    29. J. L. Hoyt, H. M. Nayfeh, S. Enguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, D. A. Antoniadis, “Strained Silicon MOSFET Technology,” International Electron Devices Meeting, pp. 23-26 (2002).
    30. X. Chen, K. C. Liu, Q. C. Ouyang, S. K. Jayanarayanan, and S. K. Banerjee, “Hole and Electron Mobility Enhancement in Strained SiGe Verical MOSFETs,” IEEE Transaction on Electron Device, Vol.48, No. 9, pp. 1975-1979 (2003).
    31. Y. Toivola, J. Thurn, and R. F. Cook, “Influence of deposition conditions on mechanical properties of low-pressure chemical vapor deposited low-stress silicon nitride films,” Appl. Phys. J., 94, pp. 6915-6922 (2003).
    32. S. Habermehl, “Stress relaxation in Si-rich silicon nitride thin films,” Appl. Phys. J., 83, pp. 4672-4677 (1998).
    33. A. Tarraf, J. Daleiden, S. Irmer, D. Prasai and H. Hillmer, “Stress investigation of PECVD dielectric layers for advanced optical MEMS,” J. Micromech. Microeng. 14, pp. 317-323(2004).
    34. J. W. Kim and H. W. Yeom, “Surface and interface structures of epitaxial silicon nitride in Si(111),” PHYSICAL REVIEW B 67, 035304(2003).
    35. A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koghuchi,”Local Mechamical-Stress Control (LMC): A New Technique for CMOS-Performance Enchancement,” IEEE International Electron Devices Meeting, pp. 433-436(2001).
    36. S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, etc., ”Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design,” IEEE International Electron Devices Meeting, pp. 247-250(2000).
    37. S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, etc., ”Effect of mechical stress induced by etch-stop nitride: impact on deep-submicron transistor performance,” Microelectronics Reliability, 42, pp. 201-209(2002).
    38. C. H. Ge, C. C. Lin, C. H. Ko, etc., “Process-Strained Si (PSS) CMOS Technology Featuring 3D strain Engineering,” IEEE International Electron Devices Meeting, pp. 73-76(2003).
    39. T. Ghani, M. Armstrong, C. Auth, M. Bost, etc., “A 90nm High Volume Manufacturing Lobic Technology Freaturing Novel 45nm Gate Length Strained CMOS Transistors,” intel.
    40. S. Thompson, N. Anand, M. Armstrong, C. Auth, etc., “A 90 nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 layers of Cu Interconnects, Low k ILD, and 1 μm2 SRAM Cell,” IEEE International Electron Devices Meeting, pp. 61-64(2003).
    41. K. Rim, J. Chu, H. Chen, K. A. Jenkins, etc., “Characteristics and Device Design of Sub-100 nm Strained Si N- and PMOSFETs,” Symposium On VLSI Technology Digest of Technical Papers, pp. 98-99(2002)
    42. W. D. Robert and H. C. Chang, “Technology Limits and compact model for SiGe Scaled FETs,” NSTI-Nanotech, Vol. 2, pp. 52-55(2004).
    43. K. Ikeda, Y. Yamashita, A. Endoh, etc., “50-nm Gate Schottky Source/Drain p-MOSFETs With a SiGe Channel” IEEE ELECTRON DEVICE LETTERS, Vol. 23, No. 11, pp. 670-672(2002)
    44. Y. C. Yeo, V. Subramamian, J. Kedzierski, P. Xuan, T. J. King, J. Bokor, and C. Hu, “Nanoscale SiGe-Channel Ultra-Thin-Body Silicon-on-Insulator P-MOSFETs” International Semiconductor Device Research Symposium, Charlottesville VA, pp. 295-298(19990)
    45. Y. C. Yeo, V. Subramanian, J. Kedzierski, etc., “Design and Fabrication of 50-nm Thin-Body p-MOSFETs With a SiGe Heterostructure,” IEEE TRANSATIONS ON ELECTON DEVICES, Vol. 49, No. 2, pp. 279-286(2002)
    46. B. S. Doyle, S. Datta, M. Doczy, S. Hareland, etc., “High Performance Fully-Depleted Tri-Gate CMOS Transistors,” IEEE ELECTRON DEVICE LETTERS, Vol. 247, No. 4, pp. 263-265(2003).
    47. C. H. Chang, C. T. Peng, K. N. Chiang, “Investigation of Local-strain Effect of Nano-Scale Triple-Gate Si/SiGe CMOS Transistor,” The 3rd Cross-Strait Workshop on Nano Science and Technology (CSWNST-3), Hualien, Taiwan, 27-29 April(2004)

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE