當量產電路顯示出大量的製程變異迫使先進製程面臨了比以往更嚴厲的挑戰，因此製程變異的考量對於保證高參數時序良率更顯重要。而在IC設計階段中，快速估計安插緩衝器後之連線延遲可輔助在區塊擺置或公域繞線時進行更精準且快速的線路擺放及時序分析。在這篇論文中，我們推導出具製程變異及緩衝器安插障礙影響考量之連線延遲估算其一次近似標準式。我們的經驗顯示：一個現存不具製程變異考量的方法若採用最壞情況（平均值加3倍標準差）作延遲估計，結果會顯得過份悲觀並因此導致不必要的設計反轉。實驗結果也顯示我們的估計方法平均誤差為4%，卻能比一個目前最先進的實際安插緩衝器方法快達149倍。

Advanced process technologies impose more significant challenges especially when manufactured circuits exhibit substantial process variations. Consideration of process variations becomes critical to ensure high parametric timing yield. During the design stage, fast estimation of the achievable buffered delay can navigate more accurate and efficient wire planning and timing analysis in floorplanning or global routing. In this thesis, we derived approximated first-order canonical forms for buffered delay estimation which considers the effect of process variations and the presence of buffer blockages. We empirically show that an existing deterministic delay estimation using 3-sigma values will be over-pessimistic and thus result in unnecessary design rollback. The experimental results also show that our method can estimate buffered delay with 4% average error but achieve up to 149 times speedup when compared to a state-of-the-art statistical buffer insertion method.

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