在電晶體急速微縮的時代裡，三維度立體結構的鰭式電晶體高微縮的可能性使其在先進製程中大量被採用。然而鰭式電晶體雖已達到了更短的電晶體通道與極好的操作特性，其在接觸槽、源極汲極磊晶區等部分的寄生電阻與通道電阻的比例卻大大的提升，在電晶體導通時形成不容小覷的功率消耗。且由於短通道效應的存在，傳統上用於萃取寄生電阻的量測技術逐漸失去其準確性，使的先進製程在寄生電阻微縮的領域裡失去一個精確的參考指標。
本篇論文中回顧許多傳統寄生電阻萃取方法，包含經典的接觸點萃取之凱文結構等，並對其中受短通道效應影響較弱的部分進行改良。最後的結果成功分析了鰭式電晶體中的寄生電阻，更將電晶體接觸槽 (MD)、磊晶區(Epitaxy)與源極汲極輕摻雜區(SD Extension)之電阻萃取後做比較。鰭式電晶體中寄生電阻值阻值約占總電阻的三分之一，與長通道元件相比，寄生電阻的比則更加提高。
對寄生電阻進行萃取的討論過程中另外衍伸出電流壅塞效應(Current Crowding)對電晶體寄生電阻的影響，當電流壅塞效應明顯時，電流所感受的等效寄生電阻將比電流均勻下之電阻來的大。因此若能減緩電流壅塞效應則電晶體將有機會進一步降低寄生電阻。本論文的第四章即是透過模擬軟體討論減緩電晶體電流壅塞效應的可行性，目前透過將接觸槽深入磊晶區之想法可將寄生電阻有效地降低。
本論文希望提供先進製程精確萃取短通道元件寄生電阻之方法，並透過舒緩電流壅塞效應以進一步降低。

To scale CMOS field-effect transistors (FETs) well into the sub-20nm region, multi-gate structure, such as, FinFET is adapted as the mainstream technology solution for the suppression of short channel effects. However, epitaxial S/D regions and aggressively scaled channel length lead to enhanced parasitic effect. The serious parasitic effects affect the device performance and limit the further scaling of CMOS technology . In the past decades, several extraction methodologies for characterizing the parasitic resistance from the total device resistance under conduction were proposed. In these conventional methods, constant channel mobility and constant effective channel length under different vertical field are often their basic assumptions. While comes to the generation of FinFET device, most of them then returns inaccurate value due to strong short channel effect and apparent current crowding effect.
In this work, multiple characterization methods on a series of test patterns including traditional Kelvin Structures and Cross Bridge Kelvin Structures are discussed and verified experimentally under mature FinFET processing. The new extraction methods become insensitive to constant mobility and Leff assumptions, hence more accurate and consistent results can be obtained, giving a practical overview of parasitic resistance in a FinFET device.

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