科技進步讓液晶顯示器已經在生活中越來越普及，消費者對產品的品質要求也越來越高，因此液晶顯示器產品的灰階不斷的提升來滿足消費者的需求，但隨之伴隨而來的便是成本問題，而為了解決液晶顯示器的驅動電路成本，此篇論文提出使用高線性度機制和在佈局面積上具有高度效益技術兩種解決方法。
論文中將會分兩部分介紹提出的方法，先介紹在佈局面積上具有高度效益技術，此技術是提出新的數位類比轉換器架構，有效的降低數位類比轉換器電晶體的使用，此外也將電路中不是二的冪次的數位類比轉換器合併，從中進一步化簡數位類比轉換器電路，減少電晶體的使用，佈局繞線上使用多晶矽以及氧化摻雜層來降低佈局面積，綜合以上方法達到佈局面積上具有高度效益的成果；再來介紹高線性度機制，在線性度方面提出兩種不同架構的輸入對，讓輸出緩衝器的輸入對轉導趨近於一個常數，因此當不同輸入電壓輸入時所看到的轉導會是相同的，不會讓輸入對權重失衡，使輸出緩器對於輸入電壓壓差的容忍度增加，因此使用高位元內插輸出緩衝器也能有較好的特性，並降低數位類比轉換器的位元數。
此十位元源極驅動晶片使用0.18μm的高壓製程設計電路，並操作在18V工作電壓下，使用五級的輸出負載，五顆串聯1kΩ電阻，五顆並聯60pF電容，成功顯示正負極性伽瑪曲線各1024個電壓，證實此篇論文透過使用高線性度機制和在佈局面積上具有高度效益技術，兩種方法有效降低源級驅動器面積。

With new technological advances, liquid-crystal display (LCD) has gained universal and consumers expect higher quality product. Nowadays, industry constantly increases the gray scale of LCD to satisfy consumer’s requirements, those results to higher product cost. This thesis proposes high linearity mechanism and high efficiency of layout area technique to achieve low-cost and high performance prototypes.
This thesis presents two proposed methods in sequence. First, the thesis introduces high efficiency of layout area technique. In this method, the proposed architecture of digital-to-analog converter could effectively reduce the number of transistors. Moreover, the proposed architecture combines two digital-to-analog converters, which number is not the power of two, into one digital-to-analog converter. In layout floor plan, poly and oxide diffusion layers were mainly used for routing, that could minimize the layout area. To sum up, high efficiency of layout area has been achieved by proposed architecture and routing skills. Second, the thesis introduces high linearity mechanism. In this method, two types of input pair have been proposed. The two types of proposed input pair have advantages on making transconductance approximately constant. As a result, the transconductance is almost constant with different input voltages. Last but not least, this method increases the tolerance of buffer input voltages. Thus, buffer could be designed with more bits to interpolate the input voltages and reduce the bits of digital-to-analog converter.
These 10-bit source driver chips are fabricated in a 0.18μm high voltage process and operate at 18V supply voltage. These chips are measured under output loading which is five 1 kΩ series resistances and five 60 pF shunt capacitances. The experimental results demonstrate that, the chip could display each polarity 1024 voltage correctly. In conclusion, this thesis proves the proposed high linearity mechanism and high efficiency of layout area technique could achieve the low-cost and high performance requirements of 10-bit source driver.

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