研究生: |
劉格志 Ke-Chih Liu |
---|---|
論文名稱: |
Multistacked Tunneling Oxide for Nonvolatile Nanocrystal Memory Application 疊層結構穿隧層應用於非揮發性奈米晶記憶體之特性研究 |
指導教授: |
吳泰伯
Tai-Bor Wu |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 材料科學工程學系 Materials Science and Engineering |
論文出版年: | 2008 |
畢業學年度: | 96 |
語文別: | 英文 |
論文頁數: | 103 |
中文關鍵詞: | 疊層穿隧層 、奈米晶記憶體 、非揮發性 |
外文關鍵詞: | multistack, tunneling oxide, nanocrystal memory, nonvolatile |
相關次數: | 點閱:54 下載:0 |
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In recent years, Flash memory has been used extensively in digital storage devices, such as memory cards, USB storage device, MP3 audio player, and so on [11], [12]. Moreover, portable electrical products will demand even more nonvolatile memories with high density, fast programming / erasing speed, excellent endurance and retention characteristics. Based on these demand, the market of Flash memory will increase in a foreseeable future. However, poly-silicon floating gate in conventional Flash memory is suffered from the charge leakage through the local defect in tunneling oxide. Therefore, separated charge storage elements, such as nanocrystals embedded in MOSFET, i.e. nanocrystal memory, were studied extensively in recent years [1-5]. Moreover, to further improve the programming/erasing speed without sacrificing the retention performance, a concept of “nanocrystal memory embedded with asymmetric band engineering of tunneling oxide” is proposed in this work. We set up two series of experiments, one is the Au nanocrystal memory using SiO2-HfO2-Al2O3 (namely SHA) multistacked tunneling oxide, the other is the Au nanocrystal memory using Al2O3-HfO2-Al2O3 (namely AHA) multistacked tunneling oxide with different thickness variation. The results and discussion will be described in chapter 4 and chapter 5 in detail.
In these experiments, high-κ thin films were deposited using atomic layer deposition (ALD) to make sure the uniformity of our films. Subsequently, Au thin films were deposited using RF sputtering, and then annealed in N2 ambiance at 500oC and 650oC for SHA and AHA, respectively. Moreover, to increase the voltage drop on tunneling oxide to further improve the programming/erasing efficiency, ALD-Al2O3 control oxide were used in this work. Finally, Pt top electrode and bottom electrode were capped to form the MOS capacitor structure.
After the fabrication of devices were accomplished, C-V curve and retention characteristics were measured by HP 4285 LCR Precision Meter, I-V curve were measured using Keithley 4200, erasing speed were measured by connecting the Agilient 81110A pulse generator and HP 4285 LCR Precision Meter, and the microstructure analysis were accomplished by HRTEM images.
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