使用混合驅動多位元正反器進行功耗導向之擺置修正

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研究生：	賴御誠 Lai, Yu-Cheng
論文名稱：	使用混合驅動多位元正反器進行功耗導向之擺置修正 Power-Driven Placement Refinement Using Mixed-Driving Multi-Bit Flip-Flops
指導教授：	王廷基 Wang, Ting-Chi
口試委員:	麥偉基 Mak, Wai-Kei 陳勝雄 Chen, Sheng-Hsiung
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2023
畢業學年度：	111
語文別：	英文
論文頁數：	30
中文關鍵詞：	多位元正反器、混合驅動多位元正反器、擺置修正、功耗導向
外文關鍵詞：	Multi-Bit Flip-Flops, Mixed-Driving Multi-Bit Flip-Flops, Placement Refinement, Power-Driven
相關次數：	點閱：106 下載：0
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想要在循序邏輯電路中降低功耗，最小化時序功率是其中一項達成目標的手段。在過去幾年裡，有很多的方法被提出與應用來盡可能達成這項目標，其中之一就是使用多位元正反器取代單位元正反器，主要是因為訊號的電力消耗與其切換狀態的頻率有高度相關性，而時序有關的訊號在每個週期都會切換其狀態。這項研究欲探討在一個給定的已擺置之設計生成混合驅動多位元正反器的可能性，並以功耗做為目標導向。在我們的方法中，在額外的縮小正反器步驟前生成多數的混合驅動多位元正反器，並且可以透過額外的縮小正反器步驟來進一步取得更好的結果。實驗結果顯示這項研究提出的方法在正反器數量、正反器功耗與正反器面積的指標上領先前一個研究。

To reduce the power consumption in sequential circuits, minimizing the clock power is one of the targets. Over the years, multiple efforts and approaches have been applied, and one of them is to replace Single-Bit Flip Flops (FFs) with Multi-Bit Flip Flops (MBFFs). The power consumption of a signal is highly related to its switching rate, and the clock signal in each FF switches its state every cycle. This work explores the possibilities of generating mixed-driving MBFFs from a given placement, and presents a power-driven approach for it. In our approach, most mixed-driving MBFFs are generated before the additional downsizing procedure, while the downsizing procedure is used to downsize MBFFs further to achieve better results. The experimental results show that the proposed approach outperforms a prior one in number of sinks, flip flop power, and flip flop area.

Acknowledgements
摘要 i
Abstract ii
Introduction 1
1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Related Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Problem Formulation 5
Proposed Approach 7
1 Overall Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Extraction of Flip Flop Information . . . . . . . . . . . . . . . . . . . . . . . 8
3 Feasible Region Generation of Each Flip-Flop . . . . . . . . . . . . . . . . . . 9
4 Finding Maximal Cliques in Rectangle Intersection Graph . . . . . . . . . . . 10
5 Mixed-Driving MBFF Selection . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 Location Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7 Mixed-Driving MBFF with Empty Bits . . . . . . . . . . . . . . . . . . . . . 16
8 Timing-Driven MBFF Downsizing . . . . . . . . . . . . . . . . . . . . . . . . 16
Experimental Results 19
1 Experimental Environment and Parameters Setup . . . . . . . . . . . . . . . . 19
2 Comparing The Number of Sinks, Flip Flop Power, and Flip Flop Area with
Mean Shift [1] and [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 Clock Tree Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 Considering Signal Switching Power . . . . . . . . . . . . . . . . . . . . . . . 24
5 Considering Mixed-Driving MBFF with Empty Bits . . . . . . . . . . . . . . . 26
Conclusion and Future Works 27
1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
References 29
                                

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