隨著科技發展的進步，現代通訊用電子產品如手機、路由器、藍牙無線耳機、智慧家電等不只朝向更高傳輸資料率，同時也朝向系統單晶片(System On Chip, SoC)的方向發展。本研究提出一個應用於光通訊SONET OC-192規格之單晶片時脈與資料回復電路，旨在因應更高資料率的同時也達到SoC的優點。

電路實現上，壓控振盪器須於相位雜訊與面積之間做取捨，本研究採用四級環形振盪器，以產生相位差90度的5 GHz時脈對10 Gbps資料做半速率取樣；以二元相位偵測器來達到高速且零死區的操作；電荷泵中設計動態電流補償機制改善迴路鎖定時UP/DN電流之匹配度，以達到單晶片整合、高資料率、低抖動的特點。

本論文電路以TSMC 90nm 1P9M CMOS製程實作，晶片面積包含ESD、PAD與On-chip Loop Filter為1.894 × 1.339 mm2。在1.2 V供應電源下，功率消耗為164 mW。以HSPICE模擬於PRBS7輸入資料下符合OC-192之Jitter Generation規格；以Matlab/Simulink數學軟體模擬迴路頻寬與抖動峰值符合OC-192定義之Jitter Transfer Function規格。

As the technology develops, modern communication electronic products such as mobile phones, routers, Bluetooth wireless earphones, and smart home appliances are not only evolving towards higher data rates but are also progressing in the direction of System on Chip (SoC) integration. This study proposes a single-chip clock and data recovery (CDR) circuit for optical communication applications meeting the SONET OC-192 standard, aiming to achieve the benefits of SoC implementation while meeting the demands of higher data rates.

In circuit implementation, a trade-off between phase noise performance and layout area has to be considered in the voltage-controlled oscillator (VCO) design. A four-stage ring oscillator was adopted to generate a 5 GHz quadrature clock for half-rate sampling of 10 Gbps data. A binary phase detector was chosen to achieve high-speed operation without dead zone issue. Furthermore, a dynamic current compensation mechanism was used in the charge pump to reduce the UP/DN current mismatch during loop locking, thereby achieving the features of single-chip integration, high data rate, and low clock jitter.

The proposed circuit was realized using TSMC 90 nm 1P9M CMOS technology, with a total chip area (including ESD, PAD, and On-chip Loop Filter) of 1.894 × 1.339 mm2. Under a 1.2 V supply voltage, the total power consumption is 164 mW. HSPICE simulation result with PRBS7 input data meets the OC-192 Jitter Generation specification, while MATLAB/Simulink simulation demonstrates that the loop bandwidth and jitter peaking meet the requirements of the OC-192 Jitter Transfer Function specification.