隨著積體電路和無線通訊技術的迅速發展，行動通信的使用愈來愈普及，服務內容也趨於樣化，第三代行動通訊服務也因應而生。
第三代行動通訊使用寬頻分碼多工多重擷取(wideband code-division multiple access, W-CDMA)的技術，性能與規格遠高於目前普遍使用的GSM系統，可提供即時影像應用、網路瀏覽、行動多媒體等各種應用，屆時2G單純的語音服務將被3G提供的語音與數據整合服務所取代。
近年來，由於CMOS製程的進步，深次微米(deep sub-micro)技術允許CMOS電路的工作頻率超過5 GHz，大大提高CMOS射頻(radio frequency, RF)電路與基頻數位訊號處理電路整合的可能性，如此一來，將可以大幅提高接收器之系統性能，降低功率消耗、成本及體積，達成系統單晶片(system on a chip, SOC)之設計目標。
於本論文中，藉由分析3GPP規範之各項測試條件，推導出應用於W-CDMA使用者裝備端之射頻接收器的規格，經由每一項測試條件，可定義出系統射頻特性例如雜訊指數，三次項交互調變失真及相位雜訊等，並藉由這些分析來最佳化接收器各子電路特性。
於本論文中，吾人亦介紹應用於2千兆赫W-CDMA之整數型頻率合成器的設計，包含壓控振盪器、相位頻率檢測器、充電泵、迴路濾波器及除頻器。頻率合成器以台積電CMOS 0.18微米1P6M製程為載具實現，提供5兆赫頻寬，於1.8伏特之操作電壓下，僅消耗21.6毫瓦，切換電容式壓控振盪器之輸出頻率可由3949兆赫至4534兆赫，偏移中心頻率8兆赫處之相位雜訊為-138 dBc/Hz。

In this thesis, RF receiver requirements for W-CDMA user equipment are derived from the analysis of the test conditions in the recent 3GPP standard. From each test condition, we could define system-level RF characteristics such as noise figure, IIP3, phase noise, etc. On the basis of these analyses, we performed some optimization on the performance of each receiver component.
The design of an integer-N frequency synthesizer for 2-GHz W-CDMA applications is also presented in this thesis, including voltage controlled oscillator, phase frequency detector, charge pump, loop filter and divider. Realizing in a TSMC CMOS 0.18 um one-poly six-metal (1P6M) technology, the synthesizer provides a channel spacing of 5 MHz while dissipating 21.6 mW from 1.8 V power supply. The switched capacitor VCO has output frequency from 3949 MHz to 4534 MHz with phase noise -138 dBc/Hz at 8 MHz offset.

參考文獻
[1] Behzad Razavi, “RF Microelectronics,” Prentice Hall Series in Mobile Communication, 1998.
[2] Behzad Razavi, “Design Considerations for Direct-Conversion Communications,” IEEE Trans. Circuits Syst. II, vol. 44, pp. 428-435, June 1997.
[3] J. H. Mikkelsen, T. E. Kolding, T. Larsen, T. Klingenbrunn, K. I. Pedersen, and P. Mogensen, “Feasibility Study of DC Offset Filtering for UTRA-FDD/WCDMA Direct-Conversion Receiver,” in Proc. 17th IEEE NORCHIP Conf., Oslo, Norway, Nov. 1999, pp. 34-39.
[4] http://www.muruta.com
[5] Third Generation Partnership Project (3GPP), “UE Radio Transmission and Reception (FDD),” Technical Specification 25.101, Vol. 3.0.0, October 1999.
[6] Bala Ramachandran, John Vasa, and Aravind Loke, “Key Specifications and Implementation of WCDMA Receiver,” Proceedings of the 2001 International Symposium on VLSI Technology, Systems, and Applications, pp.49-52, April 2001.
[7] O. K. Jensen, T. E. Kolding, C. R. Iversen, S. Laursen, R. V. Reynisson, J. H. Mikkelsen, E. Pedersen, M. B. Jenner, and T. Laursen, “RF Receiver Requirements for 3G W-CDMA Mobile Equipment,” Microwave J., pp.22-46, Feb. 2000.
[8] http://www.sawnics.com
[9] Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGRAW-Hill international edition, 2001.
[10] W. O. Keese, “An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL’s,” National Smiconductor Application Note, no. 1001, July. 2001.
[11] J. C. Bor, “Course-Related Materials,” Department of Electrical Engineering, National Tsing-Hua University.
[12] D. B. Leeson, “A Simple Model of Feedback Oscillator Noises Spectrum,” proc. IEEE, vol 54, pp. 329-330, Feb. 1966.
[13] A. Hajimiri, and T. H. Lee, “Oscillator Phase Noise: a Tutotrial,” IEEE J. Solid-State Circuits, vol. 32, pp. 326-336, March. 2000.
[14] Bram De Muer, M. Borremans, M. Steyaert, and G. Li Puma, “A 2-GHz Low-phase-noise Integrated LC-VCO Set with Flicker-noise Upconversion Minimization,” IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1034-1038, July 2000.
[15] Pietro Andreani, and Sven Mattisson, “On the Use of Mos Varactors in RF VCO’s,” IEEE J. Solid-State Circuits, vol. 35, pp. 905-910, June. 2000.
[16] J. Rogers, J. Macedo, and C. Plett, “The Effect of Varactor Nonlinearity on Phase Noise of Completed Integrated VCOs,” IEEE J. Solid-State Circuits, vol. 35, pp. 1360-1367, Sept. 2001.
[17] M. Rachedine, A. Das, M. Shah, J. Mondal, and C. Shurbboff, “Performance Review of Integrated CMOS VCO Circuits for Wireless Communications,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 77-80, 2003.
[18] R. B. Merrill et al., “Optimization of High Q Integrated Inductors in Multi-level Metal CMOS,” IEDM Tech. Dig., pp.983-986, Dec. 1995.
[19] M. Park et al., “High Q Microwave Inductors in CMOS Double-metal Technology,” IEDM Tech. Dig., pp. 59-62, Dec. 1997.
[20] D. Lovelace, N. Camilleri, and G. Kannel, “Silicon MMIC Inductor Modeling for High Volume, Low Cost Applicationsd,” Microwave J., pp 60-71, Aug. 1994.
[21] C. M. Hung, B. A. Floyd, N. Park, and K. O. Kenneth, “Fully Integrated 5.35-GHz CMOS VCOs and Prescalers,” IEEE Trans. Microwave Theory Tech., vol. 49, no. 1, pp. 17-22, Jan. 2000.
[22] Neric H. W. Fong, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, and N. Garry Tarr, “Design of Wide-band CMOS VCO for Multiband Wireless LAN Applications,” IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1333-1342, Aug. 2003.
[23] Zhenbiao Li, and Kenneth O, “A 900-MHz 1.5-V CMOS Voltage-Controlled Oscillator Using Switched Resonators with a Wide Tuning Range,” IEEE Microwave and Wireless Components Letters, vol. 13, no. 4, pp. 137-139, April 2003.
[24] Domine M. W. Leenaerts, Cicero S. Vaucher, Hank Jan Bergveld, Michael Thompson, and Kevin Moore, “A 15-mW Fully Integrated I/Q Synthesizer for Bluetooth in 0.18-um CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1155-1162, July 2003.
[25] Yuan-Kai Chu, and Huey-Ru Chuang, “A Fully Integrated 5.8 GHz U-NII Band 0.18-um CMOS VCO,” IEEE Microwave and Wireless Components Letters, vol. 13, no. 7, pp. 287-289, July 2003.
[26] A. Kral, F. Behbahani, and A. A. Abidi, “RF-CMOS Oscillators with Switched Tuning,” Custom IC Conf., May 1998, pp. 555-558.
[27] Tsung-Hsien Lin, and William J. Kaiser, “A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 424-431, March 2001.
[28] R. E. Best, “Phase –Locked Loops: Theory, Design, and Applications,” New York: McGraw-Hill, 1984.
[29] H. Kondoh, H. Notani, T. Yoshimura, H. Shibata, and Y. Matsuda, “A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Detector,” IEICE Trans. Electron., vol. E78-C, no. 4, pp. 381-388, Apr. 1995.
[30] G. B. Lee, P. K. Chan, and L. Siek, “A CMOS Phase Frequency Detector for Charge Pump Phase-Locked Loop,” Circuit and System, vol. 2, pp. 601-604, Aug. 1999.
[31] Jae-Shin Lee, Min-Sun Keel, Shin-II Lim, and Suki Kim, “Charge Pump with Perfect Current Matching Characteristics in Phase-Locked Loops,” ELECTRONICS LETTERS, 9th, vol. 36, no. 23, pp. 1907-1908, Nov. 2000.
[32] W. Rhee, “Design of High-Performance Charge Pumps in Phase-Locked Loops,” IEEE Press, 1999.
[33] C. Y. Wu, “A 1.5V 5GHz Dual-Band Frequency Synthesizer,” MS Thesis, Institute of Electronics Engineering, National Tsing-Hua University, June 2002.
[34] K. Ware et al., “A 200-MHz CMOS Phase-Locked Loop with Dual Detectors,” IEEE J. Solid-State Circuits, vol.24, no. 6, pp. 1560-1568, Dec. 1989.
[35] Behzad Razavi, “Design of Integrated Circuits for Optical communications,” McGraw-Hill international edition, 2003.
[36] S. Pellerano et al., “A 13.5-mW 5-GHz Frequency Synthesizer With Dynamic-Logic Frequency Divider,” IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 378-383, Feb. 2004.
[37] J. N. Soares, and W. A. M. Van Noije, “A 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC),” IEEE J. Solid-State Circuits., vol. 34, pp. 97-102, Jan. 1999.
[38] Q. Huang, and R. Rogenmoser, “Speed Optimization of Edge-Triggered CMOS Circuits for Gigahertz Single-Phase Clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456-465, Mar. 1996.
[39] A. Lehner, R. Weigel, D. Sewald, H. Eichfeld, and A. Hajimiri, “Design of a Novel Low-Power 4th-Order 1.7 GHz CMOS Frequency Synthesizer for DCS-1800,” IEEE International Symposium on Circuits and Systems, vol. 5, pp. V-637-V640, May 2000.
[40] Cicero S. Vaucher, “Architectures for RF Frequency Synthesizers,” Kluwer Academic Publishers, 2002.
[41] Dean Banerjee, “PLL Performance, Simulation, and Design, 3rd Edition,” National Semiconductor Handbook, 2003.
[42] http://www.rakon.com
[43] C. K Chiu, “Design and Realization of CMOS RF Frequency Synthesizers,” MS Thsis, Graduate Institute of Electronics Engineering, National Taiwan University, June 2001.