這篇論文提出了一個以標準元件庫內的元件為基礎建構的全數位抖動量測電路，其核心電路MIN MAX類比數位轉換器是由傳統的脈衝寬度衰減類比數位轉換器改良而來。雖然需要付出的面積代價是傳統脈衝寬度衰減類比數位轉換器的2.5倍，但MIN MAX類比數位轉換器的實現是不可小覷的。最主要的特色是能夠在一個指定的測量時段內，即時地回報待測時脈訊號的峰對峰值抖動並且不需要參考時脈訊號。更具體地說，提出的抖動量測電路可以量化待測時脈訊號所有輸入週期的資訊，即使這些週期樣本是被連續輸入的。 因此，相較於傳統的抖動量測電路，我們所提出的解決方案可以節省94.3%的資料處理時間。
所提出的解決方案已經被實現在90奈米製程下，且為了更貼近實際情況，加入了我們實驗室發表的全數位鎖相迴路用以產生的待測時脈訊號供抖動量測電路測量。根據電晶體層級的模擬，實驗數據顯示提出的MIN MAX類比數位轉換器測量待測時脈訊號峰對峰值抖動所得到的相對數位碼與待測時脈訊號的峰對峰值抖動呈現高度正相關。 此外，實驗結果也顯示我們只需要付出所提出抖動量測電路7.0%的面積去建立一個用於調整全數位鎖相迴路內濾波器參數的回授調整電路，那麼我們能夠獲得潛在的峰對峰抖動減少量是21.3%。

This thesis proposes a cell-based all-digital jitter measurement circuit based on the standard cell library. The core circuit of the MIN MAX time-to-digital converter is an improvement from the traditional pulse-shrinking based time-to-digital converter. Although the area overhead is 2.5 times that of the traditional pulse-shrinking based time-to-digital converter, the implementation of the MIN MAX time-to-digital converter is non-trivial. The most important feature is that it can report the peak-to-peak jitter of the clock under measurement within a specified measurement interval in real time and does not need reference clock. Specifically, it can derive the all-period information of clock under measurement, even if the period samples are inputted continuously. Therefore, our solution can save 94.3% of the data processing time compared to conventional jitter measurement.
The proposed solution has been implemented in the 90-nm CMOS process, and in order to get closer to the actual situation, we have imported an all-digital phase-locked loop (ADPLL) published by our laboratory to generate the clock under measurement for the jitter measurement circuit. According to the transistor level simulation, the experimental data shows that the relative digital code obtained by the proposed MIN MAX time-to-digital converter to measure the peak-to-peak jitter of the clock under measurement is highly positively correlated with the peak-to-peak jitter of the clock under measurement. Moreover, the experimental results also show that we only require the 7.0% area overhead of proposed jitter measurement for feedback tuner which is used to tune the parameter of loop filter of ADPLL, then we can acquire the potential peak-to-peak jitter reduction is 21.3%.

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