本研究是呈現一具有阻抗不匹配與消除反射波功能的5Gbps傳輸器於0.18 CMOS製程的設計與實現。在電路中使用2:1多工器將一對半週期架構的資料合成一個5Gbps的偽隨機二進制序列。並使用等化器最多可以降低兩個單位時間的碼間干擾。在消除反射波功能部分則最多可以消除八個單位時間的反射波。在終端阻抗部分則使用P型金屬氧化物半導體場效電晶體陣列搭配數位控制以調整阻值，可調整阻值範圍為25歐姆至1350歐姆。可以藉由調整阻值，來達到更大的電壓振幅，可因此降低功率消耗。因為調整阻值而造成阻抗不匹配進而產生反射波，可藉由消除反射波功能來降低其影響。此架構所設計之消除反射波功能，可消除1至64個週期，最小可消除之反射波為85uA乘上當下所選擇之阻值。此傳輸器是使用0.18u CMOS製程，當操作在3.6Gbps時，在傳輸器端使用150歐姆的終端阻抗以及在接收端使用1M歐姆終端阻抗，並消除在八個週期後的反射波，所消耗的總功率為166.94毫瓦。

This thesis presents a chip-to-chip transmitter with tunable termination and reflection cancellation function. The transmitter has one 2:1 mux in the data path combining two half-rate data streams into one for a total 5Gbps. There are two taps for pre-emphasis to cancel ISI(Inter Symbol Interference) and eight taps to cancel reflection. The termination is a PMOS array for a tuning range from 25ohm to 1350ohm by digital control. By changing the termination to the right trend, the output swing could become lager, and then can lower down the power consumption. The reflection caused by mismatching termination can be cancelled by reflection cancelling taps. The structure is designed to cancel the reflection between 1 to 64 clock cycle. The resolution of cancellation depends on the termination we chosen multiply the minimum current of 85mA. The transmitter is implemented by 0.18um CMOS technology. The total power is 166.94mW with 150ohm at transmitter and 1Mohm at receier when cancelling a reflection after 8 clock cycles at 3.6Gbps.

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