二維半導體在未來奈米電子領域展現出極大潛力，然而其元件的穩定性常因缺陷的電荷捕捉而受限。本研究利用脈衝量測與噪音分析，探討 WS₂ 電晶體中的缺陷機制，同時比較加入 hBN 緩衝層與僅使用 SiO₂ 基板在效能改善上的影響。

本研究所使用的 FET 元件是透過塊材機械剝離、電子束微影與乾式轉印等製程製作而成，並針對有無 hBN 緩衝層的元件，在不同溫度與閘極偏壓下進行脈衝與噪音分析。結果顯示，雖然引入 hBN 緩衝層會略微降低電流表現，但能減輕汲極電流的不穩定衰減，提供較穩定的系統。此外，脈衝與雜訊分析結果指出，系統中主要存在兩種缺陷捕捉機制：在低溫下，捕捉過程主要受到介電質中均勻分布缺陷的穿隧效應主導，導致固定的時間常數與噪音頻譜呈現斜率為 −1 的典型 1/𝑓 噪音行為；而在高溫環境下，捕捉機制則轉為受 WS₂ 本身的能隙內缺陷主導，呈現電壓相關的時間常數，並在噪音頻譜中出現近似 −2 的斜率。

本研究透過同時結合動態脈衝量測與靜態雜訊分析，深入解析 WS₂ 電晶體中的動態行為，提供探索二維電晶體缺陷機制新穎的研究方法與見解。

Two-dimensional semiconductors show potential for future nanoelectronics but suffered from charge trapping, which degrades device performance and stability. This study investigates the trap mechanisms in WS₂ FETs using pulse measurements and noise analysis, meanwhile comparing the effects of an additional hBN buffer layer with intrinsic SiO₂ substrates on performance improvement.

FETs were fabricated using mechanical exfoliation, electron-beam lithography, and dry transfer process. Devices with and without hBN buffer layer were both analyzed under various temperatures and gate voltages. Results show that although the inclusion of hBN buffer layer slightly reduces current performance, it can mitigate drain current degradation, contributing to a more stable system.

According to the pulse measurements and noise analysis, two primary trap transition pathways exist in the system. At low temperatures, transitions are dominated by tunneling to dielectric traps, resulting in a constant time constant and a −1 slope in noise spectrum. While under higher energy, the transition mechanism is dominated by intrinsic bandgap traps in WS₂, leading to a voltage-dependent time constant and a nearly −2 slope in noise spectrum.

By simultaneously analyzing the electrical properties of 2D FETs through dynamic pulse measurements and static equilibrium noise analysis, this study provides new insights into WS₂ FETs transient behavior, offering a novel approach to study trap dynamics in 2D FETs.