減少邏輯電路中的及閘數量有益於密碼學、安全、量子計算等領域的應用。目前針對這個優化問題提出的最先進的方法是套用一個包含重寫、重構和重新替換等技術的合成流程。雖然實驗結果令人印象深刻，但仍然遺留許多能夠進一步優化的機會。在此論文中，我們提出了一個利用邏輯無關項來減少邏輯電路中及閘數量的方法。此外，我們也提出一個結合最先進的方法的增強式合成流程。實驗使用的測試電路是來自洛桑聯邦理工學院和密碼學領域，並且經過之前研究方法的優化。實驗結果顯示，我們的方法能進一步減少邏輯電路中至多25\%的及閘數量。而對於增強式合成流程的實驗，相較於最先進的方法，在密碼學的測試電路集中，我們達到將近十倍的加速，並擁有和其抗衡的優化結果。

Reducing the number of AND gates in logic networks benefits the applications in cryptography, security, and quantum computing. The state-of-the-art to this optimization problem applied a synthesis flow including rewriting, refactoring, and resubstitution. Although the result was impressive, there remained some opportunities to be optimized further. This work proposes a don’t-care-based approach to reduce the number of AND gates further in the network. Furthermore, this work also proposes an enhanced synthesis flow by integrating our approach with the state-of-the-art. The experiments were performed on a set of well-optimized EPFL and cryptography benchmarks obtained by previous works. The experimental results show that our approach can further reduce up to 25\% of the number of AND gates in the network. For the experiments about the enhanced synthesis flow, we achieve a speedup of almost 10X on average for the cryptography benchmarks while having competitive results as compared to the flow in the state-of-the-art.

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