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研究生: 吳奇達
Chi-Ta Wu
論文名稱: 低功率數位訊號處理器之指令緩衝器設計
Instruction Buffering For Low Power Design
指導教授: 黃婷婷
TingTing Hwang
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2001
畢業學年度: 89
語文別: 英文
論文頁數: 40
中文關鍵詞: 指令緩衝
外文關鍵詞: Instruction Buffering, DIB, LCC, Low Power, nested-loop, Loop Buffer Controller, ATOM, Wattch
相關次數: 點閱:133下載:0
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  • 在這篇論文中,我們根據數位訊號處理機(DSP)以及Embedded Systems的程式特性----隨時隨地都在做迴圈的特性來設計一個迴圈控制器(Loop Controller)和一個Stack以及一個比main cache還小的buffer,這個控制器用來告訴CPU是否下一個指令需求(instruction request)在main cache或者在這一個比較小的Buffer.,如果這個需求在(hit) buffer,控制器就可以關掉main cache來節省能量的消耗。假設buffer存的是已解碼過的指令(Decoded Instruction Signal),控制器甚至可以關掉有關decode的Component。


    In recent years, the reduction of power consumption by the microprocessor
    and DSP has become an important design constraint. Loop buffer techniques were proposed to reduce power consumption.

    These approaches are based on two main observations.

    The first observation is that a significant fraction of power consumed

    is by memory access and instructions decode.

    The second observation is that a major fraction of dynamic instruction

    counts of many applications are from small tight loops.

    Although schemes of papers are very effective

    in reducing power, they work for the inner-most loop only.

    In this paper, we propose a stack-based controller

    which is called Loop Cache Controller (LCC).

    Our scheme can deal with nested-loop of all styles and if-then-else

    construct in a loop . At last,

    we use power estimator Wattch to estimate the power

    reduction at the instruction level. Our experiments show the reductions of

    power consumption of our technique is up to 60 \% as compared to

    power consumption of that without instruction buffering technique

    at fetch and decode stages.

    1 Instruction 2 Previous Work 3 Stack-Based Loop Buffer Controller 4 Experimental Results 5 Conclusions A The Option When Running Command sim-outorder

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