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研究生: 李傳勝
Li, Chuan-Sheng
論文名稱: 應用於微小電容變化感測之積分三角調變器
Sigma-Delta Modulator for Small-variance Capacitive Sensing Applications
指導教授: 徐永珍
Hsu, Yung-Jane
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 中文
論文頁數: 67
中文關鍵詞: 積分三角調變器電容式感測電路相關雙取樣
外文關鍵詞: Sigma-Delta Modulator, Capacitive sensing circuit, CDS
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  • 近幾年越來越多微機電感測器被應用於消費性電子產品上,而感測器開發研究又以電容式感測器最為普遍,當電容式感測器與讀出電路整合在單一晶片上時,由於電容式感測器的電容變化量相當小,所以讀出電路的設計就非常重要。
    本論文利用積分三角調變器當作一個電容數位轉換器也是一個類比數位轉換器。模擬結果最小可偵測的電容為0.1fF以及訊號對雜訊與失真比可達73dB。整體面積包含I/O PAD為0.384 mm2並實現於CMOS 0.18um製程,在1.2V的操作電壓下消耗功率為0.29mW,適合於可攜式產品之應用。


    In recent years, more and more MEMS sensors, especially the capacitive sensors, were used in consumer electronic products. The capacitive sensors have gained an increasing research interest in the last few years. The variance values of the capacitance are generally small, when the sensor and readout circuit are integrated together as a system on a chip (SoC). Therefore, the design of readout circuits are becoming more and more critical.

    The proposed sensing circuit for capacitive sensors is based on sigma-delta modulator (SDM) and can be used not only as a capacitance-to-digital convertor (CDC) but also as a analog-to-digital (ADC). The simulated results showed that the minimum detectable capacitance value and the peak SNDR are 0.1 fF and 73 dB, respectively. The chip was implemented using CMOS 0.18□m technology and occupies an area of 0.384 mm2, including I/O pads. The power dissipation is only 0.29 mW under 1.2 V voltage supply. This low power circuit is suitable for the use in portable products.

    摘要 i Abstract ii 誌謝 iii 索引 iv 第一章 緒論 1 1.1相關研究發展 1 1.2 研究目的 3 1.3 論文架構解說 4 第二章 積分三角調變器之原理介紹與模擬 5 2.1簡介 5 2.2量化雜訊與超取樣技術 6 2.3 雜訊移頻 8 2.4非理想效應 11 2.4.1 熱雜訊 11 2.4.2 Settling noise 13 2.4.3 放大器之有限增益 16 2.5 MATLAB系統模擬 17 2.6結論 20 第三章 電容數位轉換器 21 3.1 簡介 21 3.2 電容數位轉換器型式 21 3.2.1 SAR CDC 21 3.2.2 Dual-slope CDC 23 3.3 積分三角調變器之電容數位轉換器 24 第四章 積分三角調變器之電路分析與模擬 27 4.1 積分三角調變器系統架構簡介 27 4.2 具相關雙取樣電路之交換電容式積分器 28 4.3 區塊電路設計 31 4.3.1 低電壓下開關設計考量 31 4.3.2 運算放大器與偏壓電路 32 4.3.3 1-bit 量化器(Quantizer) 35 4.3.4 非重疊時脈產生器(Non-overlapping Clock Generator) 36 4.3.5 電壓倍增器(Voltage multiplier) 38 4.3.6 輸出緩衝器(Voltage multiplier) 38 4.3.7 6-bit Binary-weighted digital trimming 39 4.4模擬結果(Simulation Result) 40 4.4.2 整體電路模擬 45 4.4.3 整體電路佈局模擬 48 4.5佈局圖與佈局考量 51 4.6 結論 53 第五章 量測環境與量測結果 54 5.1 量測環境介紹 54 5.1.1 PCB量測板設計與考量 54 5.1.2 量測方法與儀器介紹 56 5.2 量測結果 57 5.2.1 晶片直流電壓量測 57 5.2.2 晶片系統量測 58 5.3 量測結果分析與討論 61 第六章 結論與後續研究建議 65 6.1 結論 65 6.2 後續研究建議 65 參考文獻 66

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