本篇論文以氧化鈰(CeO2)、氧化杉(Sm2O3)和氧化鉿(HfO2)在金氧半電容器上作為閘極絕緣層來製作以及研究。分別使用射頻磁控式濺鍍和原子層化學沉積技術來沉積閘極絕緣層。
氧化鈰(CeO2)薄膜在X光繞射儀的分析上於快速高溫退火之前就已經結晶，在電子顯微鏡的分析上也可以清楚的看到結晶以及氧化鈰(CeO2)薄膜與矽晶圓之間有產生一層界面層。
傳導機制分析之中，在Al/CeO2/p-Si結構於高溫(>350K)低電場(0.36~1.56 MV/cm)時，產生蕭特基發射機制，然而於高溫(500K)高電場(1.69~2.66 MV/cm)時，產生普爾-法蘭克發射機制。在Al/Sm2O3/p-Si結構於高電場(1.96~4 MV/cm)時，產生蕭特基發射機制。在Al/HfO2/p-Si結構於低電場(0.16~2.89 MV/cm)時，產生蕭特基發射機制。實驗結果中，可以得到能障高度，於Al/CeO2是0.478 eV 在電場1.53 MV/cm，於Al/Sm2O3是0.362 eV在電場3.1 MV/cm，於Al/HfO2是0.278 eV在電場1.6 MV/cm。不同溫度中的韋伯斜率於氧化鈰(CeO2)為6.5，於氧化杉(Sm2O3)為7.1，於氧化鉿(HfO2)為3.3，而薄膜在QBD63%的活化能方面，於氧化鈰(CeO2)為0.37 eV，於氧化杉(Sm2O3)為0.346 eV，於氧化鉿(HfO2)為0.143eV。

In this thesis, Metal-Insulator-Si (MIS) capacitors with CeO2, Sm2O3 and HfO2 gate dielectrics were fabricated and investigated. The CeO2, Sm2O3 and HfO2 gate dielectrics were deposited by RF magnetron sputtering and atomic layer chemical vapor deposition (ALD), respectively.
The XRD analysis revealed that CeO2 thin films already were polycrystalline at as-deposited, TEM analysis revealed that an interface layer (IL) was formed between the high-κ film (CeO2) and Si substrate.
The dominant conduction mechanism of Al/CeO2/p-Si structure at high temperature (>350K) is Schottky emission in low electric fields (0.36~1.56 MV/cm) and at high temperature (500K) is Poole-Frenkel emission in high electric fields (1.69~2.66 MV/cm). The dominant mechanism of Al/Sm2O3/p-Si structure at high electric fields (1.96~4 MV/cm) is Schottky emission. The dominant mechanism of Al/HfO2/p-Si structure at low electric fields (0.16~2.89 MV/cm) is Schottky emission.
Experimental results showed that the barrier height of Al/CeO2 is 0.478 eV at 1.53 MV/cm, and that of Al/Sm2O3 is 0.362 eV at 3.1 MV/cm and that of Al/HfO2 is 0.278 eV at 1.6 MV/cm. The extracted Weibull slope for different temperatures (25℃, 85℃, 125℃) is found to be 6.5 in CeO2 thin film, 7.1 in Sm2O3 thin film and 3.3 in HfO2 thin film. The activation energy of CeO2 thin film calculated from the QBD63% plots was about 0.37 eV, and it was about 0.346 eV for Sm2O3 thin film, and 0.143 eV for HfO2 thin film.

[1] H. Iwai, Solid-State Electronics, 48, pp. 479-503 (2004)
[2] International Technology Roadmap for Semiconductors Home Page,
http://public.itrs.net (2006)
[3] J. Robertson, Eur. Phys. J. Appl. Phys. 28, 265-291 (2004)
[4] H. Iwai, S. Ohmi, S. Akama, C. Ohshima, A. Kikuchi, J. Taguchi, H. Yamamoto,
J. Tonotsni, Y. Kim, I. Ueda, A. Kuriyama, and Y. Yoshihara, IEDM, p.625 (2002)
[5] Takashi Hori, Gate Dielectrics and MOS ULSIs : principles, technologies and
applications, Springer, Berlin (1997)
[6] T.K. Kundu and J. Y. Lee, J. Electrochem. Soc., 147, 326 (2000)
[7] James D. Plummer, Michael D. Deal and Peter B. Griffin, Silicon
VLSI Technology Fundamentals, Practice and Modeling, Prentice Hall (2000)
[8] S. Wolf, Silicon Processing for the VLSI Era Volume 4
-Deep Submicron Process Technology (2002)
[9] Michel Houssa, High-κ Gate Dielectrics, Taylor and Francis (2004)
[10] Hong Xiao, Introduction to Semiconductor Manufacturing Technology,
Prentice Hall (2001)
[11] X-Ray Diffraction and Scanning Probe Microscopy, 2
[12] Dieter K. Schroder , Semiconductor Material and Device Characterization
Third Edition, John Wiley and Sons, New York (2006)
[13] Fu-Chien Chiu, J. Appl. Phys. 100, 114102 (2006)
[14] S. M. Sze, Physics of Semiconductor Devices Third Edition, John Wiley and Sons, New York (2007)
[15] Muller R. S. and T. I. Kamins with Mansun Chan, Device Electronics for Integrated Circuits Third Edition, John Wiley and Sons (2003)
[16] C. Maunoury, K. Dabertrand, E. Martinez, M. Saadoune, D. Lafond, F. Pierre, O. Renault, S. Lhostis, P. Bailey, T. C. Q. Noakes, and D. Jalabert, J. Appl. Phys. 101, 034112 (2007)
[17] The Electrical Characteristics of Metal-Oxide-Semiconductor Capacitors and Metal-Oxide-Semiconductor Field Effect Transistors Using High-Dielectric-Constant Thin Film as Gate Dielectric, National Tsing Hua University, Fu-Chien Chiu (2005/06)
[18] The Electrical Properties of Zirconium Oxide Thin Films for Metal-Oxide-Semiconductor Field Effect Transistor Gate Dielectric Applications, National Tsing Hua University, Ming-Tso
[19] J. G. Simmons, Phys. Rev. 155, 657 (1967)
[20] J. R. Yeargan and H. L. Taylor, J. Appl. Phys. 39, 5600 (1968)
[21] Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand,
Proc. of IEEE, 305 (2003)
[22] Takashi Hori, Gate Dielectrics and MOS ULSIs : principles, technologies and applications, Springer, Berlin (1997)
[23] Yuan Taur and Tak H. Ning, Fundamentals of Modern VLSI Devices (1998)
[24] Michel Depas, Tanya Nigam and Marc M. Heyns, IEEE Tran. Electron Devices 43, 1499 (1996)
[25] Takashi Hori, Gate Dielectrics and MOS ULSIs : principles, technologies
and applications, Springer, Berlin (1997)
[26] S. Wolf, Silicon Processing for the VLSI Era Volume 3-The Submicron MOSFET (1995)
[27] R. Degraeve, J. L. Ogier, R. Bellens, P. J. Roussel, G. Groeseneken, H. E. Maes,
ED, p. 472 (1998)
[28] S. Wolf, Silicon Processing for the VLSI Era Volume 4-Deep Submicron Process Technology (2002)
[29] J. H. Stathis, IBM J. RES. & DEV. Vol. 46 p.265 (2002)
[30] M. Kimura, IEEE Tran. Electron Devices 46, 220 (1999)
[31] A. M. Yassine, H. E. Nariman, M. McBride, M. Uzer, and K.R. Olasupo, IEEE Tran. Electron Devices 47 1416 (2000)
[32] Materials Science and Engineering C 23 (2003) pp. 1013-1016
[33] Chem. Vap. Deposition (2003) 9, No. 4
[34] A. M. Yassine, H. E. Nariman, M. McBride, M. Uzer, and K.R. Olasupo, IEEE Tran. Electron Devices 47 1416 (2000)