利用矽穿孔(Through Silicon Via, TSV)技術於三維或2.5維等集成電路能有效增進電路效能和功率。但在三維或2.5維堆疊晶片系統中，熱與熱機械問題非常嚴重。其中最嚴重的問題在製造過程以及操作過程中會碰到的熱循環。對於結構複雜的晶片而言，數種材料的差異所產生的熱膨脹，足以使得晶片中產生極大的內應力，將導致晶片產生翹曲現象，最終甚至產生斷裂等不可挽救的情形。在本論文第一個研究中，為了降低熱應力對晶片造成的破壞，不同於先前研究必須使用昂貴且非標準化之CMOS元件，我們設計了使用現有元件-微凸塊(micro bump)來減輕矽穿孔所造成的熱應力；接著，我們提供一種有效率的微凸塊擺放方法將其擺放在晶片上最適當的位置。另一方面，先前的研究提出許多有效率的矽穿孔擺放方法以減少晶片繞線時的線長，或減輕操作時的熱點問題。但在這些問題之外，在第二個研究中，我們證明矽穿孔的擺放方式亦會影響晶片的破裂與否。我們提出一種新穎的矽穿孔擺放方法，同時考量晶片製程中可靠度、繞線長度以及晶片操作時熱點問題的影響。

Three-dimensional or 2.5-dimensional integrated circuits using Through Silicon Via (TSV) can improve performance and power. However, thermal and thermal-induced mechanical problems in 3D or 2.5D stacking-die technologies are known to be more severe than those in 2D circuits. A high temperature environment during the fabrication process of TSVs leads to uncontrollable thermal expansion, which then causes a serious reliability problem, the thermal mechanical problem. This problem can result in deformation or mechanical damage to the dies. In the first work, unlike previous works applying expensive components not in the standard CMOS process, we first present to use an “off-the-shelf” component, micro bumps, to relax the thermal mechanical stress. In addition, an efficient algorithm to place micro bumps in appropriate positions is also proposed. In the second work, many researches have proposed efficient TSV placement algorithms to alleviate the hot spot problem and to reduce the wire length. However, in addition to the thermal and wire length issues, we show TSV placement can also affect die fracture. Hence, we propose a novel TSV placement approach simultaneously considering die fracture, thermal, and wire length constraints.

[1] K. Athikulwongse, A. Chakraborty, J.-S. Yang, D. Z. Pan and S. K. Lim, “Stress-Driven 3D-IC Placement with TSV Keep-Out Zone and Regularity Study,” in Proc. IEEE Int. Conf. Computer-Aided Design(ICCAD), 2010.
[2] K. B. Broberg, “Cracks and fracture,” in San Diego, CA: Academic Press, 1999.
[3] J. Cong, G. Lou and Y. Shi, “Thermal-Aware Cell and Through-Silicon-Via Co-Placement for 3D ICs,” in Design Automation Conference (DAC), 2011.
[4] B. Dang, J. U. Knickerbocker and C. K. Tsang. US Patent No. 7799613, 2010.
[5] T. Dao, D. H. Triyoso, M. Petras and M. Canonico, “Through Silicon Via Stress Characterization,” in IEEE International Conference on IC Design and Technology(ICIDT), 2009.
[6] S. Fortune, “A Sweepline Algorithm for Voronoi Diagrams”. Algorithmica 2, 153-174, 1987.
[7] B. Goplen and S. Sapatnekar, “Thermal Via Placement in 3D ICs,” in International Symposium on Physical Design (ISPD), 2005.
[8] B. Goplen and S. Sapatnekar, “Placement of 3D ICs with Thermal and Interlayer Via Considerations,” in Design Automation Conference (DAC), 2007.
[9] A. M. Howatson, P.G. Lund, J.D. Todd, “Engineering tables and data”. (2nd ed)Chapman & Hall, London,1991.
[10] G. R. Irwin, “Analysis of Stresses and Strains Near the End of a Crack Traversing a Plate,” Journal of Applied Mechanics, Vol. 24, pp 361-364, 1957.
[11] R. Iyer and L. Kleinrock, “Qos Control For Sensor Networks,” in IEEE International Conference on Communications(ICC), 2003.
[12] M. Jung, J. Mitra, D. Z. Pan and S. K. Lim, “TSV Stress-aware Full-Chip Mechanical Reliability Analysis and Optimization for 3D IC,” in Proc. ACM Design Automation Conf(DAC), 2011.
[13] M. Jung, X. Liu, S. K. Sitaraman, D. Z. Pan and S. K. Lim, “Full-Chip Through-Silison-Via Interfacial Crack Analysis and Optimization for 3D IC,” in International Conference of Computer Aided Design (ICCAD), 2011.
[14] Z. Li, X. Hong, Q. Zhou and J. Bian, “Efficient Thermal-Oriented 3D Floorplanning and Thermal Via Planning for Two-Stacked-Die Integration,” in ACM Transactions on Design Automation of Electronic Systems (TODAES), 2006.
[15] H. C. Lin and T. Y. Chang. TW Patent No. 201121375, 2011.
[16] X. Liu, Q. Chen, P. Dixit, R. Chatterjee, R. R. Tummala and S. K. Sitaraman, “Failure Mechanisms and Optimum Design for Electroplated Copper Through-Silicon Vias (TSV),” in Electronic Components and Technology Conference (ECTC), 2009.
[17] K. H. Lu, S.-K. Ryu, Q. Zhao, X. Zhang, J. Im, R. Huang and P. S. Ho, “Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects,” in Electronic Components and Technology Conference (ECTC), 2010.
[18] K. H. Lu, X. Zhang, S.-K. Ryu, J. Im, R. Huang and P. S. Ho, “Thermo-Mechanical Reliability of 3-D ICs containing Through Silicon Vias,” in Electronic Components and Technology Conference (ECTC), 2009.
[19] T. C. Lu, J. Yang, Z. Suo, A. G. Evans, R, Hecht and R. Mehrabian, “Matrix Cracking in Intermetallic Composites Caused by Thermal Expansion Mismatch,” in Acta Metall. Mater., Vol. 39, No.8, 1991.
[20] P. A. Miranda and A. J. Moll, “Thermo-Mechanical Characterization of Copper Through-Wafer Interconnects,” in Electronic Components and Technology Conference (ECTC), 2006.
[21] J. Mitra, M. Jung, S.-K. Ryu, R. Huang, S.-K Lim and D. Z. Pan, “A Fast Simulation Framework for Full-chip Thermo-mechanical Stress and Reliability Analysis of Through-Silicon-Via based 3D ICs,” in Electronic Components and Technology Conference (ECTC), 2011.
[22] C. Okoro, M. Gonzalez, B. Vandevelde, B. Swinnen, G. Eneman, S. Stoukatch, E. Beynel and D. Vandepitte, “Analysis of the Induced Stresses in Silicon During Thermcompression Cu-Cu Bonding of Cu-Through-Vias in 3D-SIC Architecture,” in Electronic Components and Technology Conference (ECTC), 2007.
[23] N. Ranganathan, K. Prasad, N. Balasubramanian and K. L. Pey, “A study of thermo-mechanical stress and its impact on through-silicon vias,” in Journal of Micromechanics and Microengineering, (13pp), 2008.
[24] S.-K. Ryu, K.-H. Lu, X. Zhang, J.-H. Im, P. S. Ho and R. Huang, “Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects,” in IEEE Transactions on Device and Materials Reliability, vol, 2010.
[25] C. S. Selvanayagam, J. H. Lau, X. Zhang, S. K.W. Seah, K. Vaidyanathan, and T. C. Chai, “Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps,” in Electronic Components and Technology Conference (ECTC), 2008.
[26] G. G. Stony, “The tension of thin metallic films deposited by electrolysis,” in Proc. R. Soc. London, A, 82, 172, 1909.
[27] M.Sunohara, H. akaguchi, A.Takano, R. Arai, K. Murayama and M. Higashi, “Studies on Electrical Performance and Thermal Stress of a Silicon Interposer with TSVs,” in Electronic Components and Technology Conference (ECTC), 2010.
[28] N. Takenao, O. Tadahiro, O. Tomotsugu and O. Tetsuya. TW Patent No. 201120995, 2011.
[29] M. Testlin, “Finite automata and modeling the simplest forms of behavior,” Ph. D. dissertation, V.A. Steklov Mathematical Institute, 1964.
[30] E. Wong and S. K. Lim, “3D Floorplanning with Thermal Vias,” in Design, Automation, and Test in Europe (DATE), 2006.
[31] P. K. Wong, F. Yu, A. Shahangian, G. Cheng, R. Sun and C. M. Ho, “Closed-loop control of cellular functions using combinatory drugs guided by a stoachastic search algorithm,” in National Academy of Sciences of the USA, 2008.
[32] J.-S. Yang, J. Pak, X. Zhao, S. K. Lim and D. Z. Pan, “Robust Clock Tree Synthesis with Timing Yield Optimization for 3D-ICs,” in Proc. Asia and South Pacific Design Automation Conf(ASP-DAC), 2011.
[33] J.-S. Yang, K. Athikulwongse, Y. J. Lee, S. K. Lim and D. Z. Pan, “TSV Stress Aware Timing Analysis with Applications to 3D-IC Layout Optimization,” in Proc. ACM Design Automation Conf(DAC), 2010.
[34] B. J. Yoon, “Enhanced stochastic optimization algorithm for finding effective multi-target therapeutics,” in BMC Bioinformatics, 2011.
[35] http://www.ansys.com
[36] http://www.xilinx.com
[37] http://opencores.org/
[38] http://www.eda.ncsu.edu/wiki/FreePDK