研究生: |
邱柏森 Chiu, Po-Sen |
---|---|
論文名稱: |
混合高度之元件與列之設計擺置合法化 Placement Legalization for Designs with Mixed-Height Cells and Rows |
指導教授: |
麥偉基
Mak, Wai-Kei |
口試委員: |
張豐願
Chang, Fong-Yuan 陳勝雄 Chen, Sheng-Hsiung 王廷基 Wang, Ting-Chi |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 資訊工程學系 Computer Science |
論文出版年: | 2019 |
畢業學年度: | 107 |
語文別: | 英文 |
論文頁數: | 31 |
中文關鍵詞: | 擺置合法化 、多重排高元件 、混和列高設計 |
外文關鍵詞: | Placement Legalization, Multiple-Row Height Cell, Mixed-Row-Height Design |
相關次數: | 點閱:3 下載:0 |
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在先進製程節點中,為了滿足各種設計需求,標準元件庫會由多重排高的標準元件所組成。在標準元件庫中,擁有多重排高的複雜標準元件通常能降低其面積。此外,在混合不同高度的列高下,也能達到更好的佈局密度與效能。考量混合列高下的多重排高元件之擺置大大提高了擺置合法化的難度。為了有效地使如此複雜的擺置合法化,我們提出了一個三階段的方法來解決混合列高佈局下的多重排高元件合法化之問題。首先,我們提出了一個基於戴克斯特拉演算法的方法來分散標準元件到擺置網格來緩和高密度區域的局部擁堵。接著,我們提出一個以窗口為基礎的方法來有效地插入標準元件至擺置區域。實驗結果顯示我們的方法能有效地使全域擺置的結果合法化且相較於[1]只在平均位移量和線長增加率擁有微小的增幅。
Standard cell libraries consisting of multiple-row-height cells have become popular in advanced process nodes to achieve various design demands. Multi-height cells are typically used to reduce the area of complex cells in a cell library. In addition, mixing different row heights may also be used for better design density
and performance. Mixed-cell-height placement with mixed row height awareness greatly increase the difficulty of placement legalization. To legalize such placement efficiently, we propose a three-stage approach to address the mixed-cell height legalization problem of mixed-row-height designs. First, we propose a method based on Dijkstra’s algorithm to spread the cells to placement bins which alleviate local congestion in high density regions. Then we propose a window-based method to insert cells into the placement region efficiently. Experimental results show that our approach can efficiently legalize global placement results with marginal quality loss compared to the work [1].
[1] C.-C. Lo, “Mixed-Height Cell Placement Legalization for Mixed-Row-Height Designs Considering Displacement and Wirelength Optimization,” Master’s thesis, National Tsing Hua University, Hsinchu, Taiwan, 2019.
[2] S.-H. Baek, H.-Y. Kim, Y.-K. Lee, D.-Y. Jin, S.-C. Park, and J.-D. Cho, “Ultrahigh density standard cell library using multi-height cell structure,” in Proc. of SPIE - The International Society for Optical Engineering, 2008.
[3] T. Chen, Z. Jiang, T. Hsu, H. Chen, and Y. Chang, “Ntuplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, pp. 1228–1240, July 2008.
[4] M. Kim, D. Lee, and I. L. Markov, “Simpl: An effective placement algorithm,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, pp. 50–60, Jan 2012.
[5] M. Hsu and Y. Chang, “Unified analytical global placement for large-scale mixed-size circuit designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, pp. 1366–1378, Sep. 2012.
[6] M. Hsu, Y. Chen, C. Huang, S. Chou, T. Lin, T. Chen, and Y. Chang, “Ntuplace4h: A novel routability-driven placement algorithm for hierarchical mixed-size circuit designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 1914–1927, Dec 2014.
7] C. Huang, H. Lee, B. Lin, S. Yang, C. Chang, S. Chen, Y. Chang, T. Chen, and I. Bustany, “Ntuplace4dr: A detailed-routing-driven placer for mixed-size circuit designs with technology and region constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, pp. 669–681, March 2018.
[8] X. He, T. Huang, L. Xiao, H. Tian, and E. F. Y. Young, “Ripple: A robust and effective routability-driven placer,” IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, vol. 32, pp. 1546–1556, Oct 2013.
[9] N. Viswanathan, M. Pan, and C. Chu, “Fastplace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control,” in 2007 Asia and South Pacific Design Automation Conference, pp. 135–140, Jan 2007.
[10] T. Lin, C. Chu, and G. Wu, “Polar 3.0: An ultrafast global placement engine,” in 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 520–527, Nov 2015.
[11] T. Lin, C. Chu, J. R. Shinnerl, I. Bustany, and I. Nedelchev, “Polar: A high performance mixed-size wirelengh-driven placer with density constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, pp. 447–459, March 2015.
[12] U. Brenner, “Vlsi legalization with minimum perturbation by iterative augmentation,” in 2012 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1385–1390, March 2012.
[13] N. Karimpour Darav, I. S. Bustany, A. Kennings, and L. Behjat, “A fast, robust network flow-based standard-cell legalization method for minimizing maximum movement,” in Proceedings of the 2017 ACM on International Symposium on Physical Design, ISPD ’17, (New York, NY, USA), pp. 141–148, ACM, 2017.
[14] N. K. Darav, I. S. Bustany, A. Kennings, D. Westwick, and L. Behjat, “Eh?legalizer: A high performance standard-cell legalizer observing technology constraints,” ACM Trans. Des. Autom. Electron. Syst., vol. 23, pp. 43:1–43:25, May 2018.
[15] M. Pan, N. Viswanathan, and C. Chu, “An efficient and effective detailed placement algorithm,” in ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., pp. 48–55, Nov 2005.
[16] W.-K. Chow, J. Kuang, X. He, W. Cai, and E. F. Young, “Cell density-drivenㄩdetailed placement with displacement constraint,” in Proceedings of the 2014 on International Symposium on Physical Design, ISPD ’14, (New York, NY, USA), pp. 3–10, ACM, 2014.
[17] G. Wu and C. Chu, “Detailed placement algorithm for vlsi design with doublerow height standard cells,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, pp. 1569–1573, Sept 2016.
[18] K.-H. Tseng, Y.-W. Chang, and C. C. C. Liu, “Minimum-implant-area-aware detailed placement with spacing constraints,” in Proceedings of the 53rd Annual Design Automation Conference, DAC ’16, (New York, NY, USA), pp. 84:1–84:6, ACM, 2016.
[19] W. Chow, C. Pui, and E. F. Y. Young, “Legalization algorithm for multiplerow height standard cell design,” in Proc. of Design Automation Conference, pp. 83:1–83:6, June 2016.
[20] Y. Lin, B. Yu, X. Xu, J.-R. Gao, N. Viswanathan, W.-H. Liu, Z. Li, C. J. Alpert, and D. Z. Pan, “Mrdp: Multiple-row detailed placement of heterogeneous-sized cells for advanced nodes,” in Proc. of International Conference on Computer-Aided Design, pp. 7:1–7:8, Nov 2016.
[21] C. Wang, Y. Wu, J. Chen, Y.-W. Chang, S. Kuo, W. Zhu, and G. Fan, “An effective legalization algorithm for mixed-cell-height standard cells,” in Proc. of Asia and South Pacific Design Automation Conference, pp. 450–455, Jan 2017.
[22] P. Spindler, U. Schlichtmann, and F. M. Johannes, “Abacus: Fast legalization of standard cell circuits with minimal movement,” in Proc. of International Symposium on Physical Design, pp. 47–53, 2008.
[23] J. Chen, Z. Zhu, W. Zhu, and Y.-W. Chang, “Toward optimal legalization for mixed-cell-height circuit designs,” in Proc. of Design Automation Conference, pp. 52:1–52:6, 2017.
[24] H. Li, W.-K. Chow, G. Chen, E. F. Y. Young, and B. Yu, “Routability-driven and fence-aware legalization for mixed-cell-height circuits,” in Proc. of Design Automation Conference, pp. 150:1–150:6, 2018.
[25] C.-Y. Hung, P.-Y. Chou, and W.-K. Mak, “Mixed-cell-height standard cell placement legalization,” in Proc. of Great Lakes Symposium on VLSI, pp. 149–154, 2017.
[26] U. Brenner, “Bonnplace legalization: Minimizing movement by iterative augmentation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, pp. 1215–1227, Aug 2013.
[27] I. S. Bustany, D. Chinnery, J. R. Shinnerl, and V. Yutsis, “Ispd 2015 benchmarks with fence regions and routing blockages for detailed-routing-driven placement,” in Proc. of International Symposium on Physical Design, pp. 157–164, 2015.