隨著製程進步，良率以及效能已經變得越來越重要。為了增加系統的良率以及效能，我們分別針對電路層級以及系統層級三個不同問題進行研究，分別為增進掃描鍊錯誤偵測率，3D-IC 的錯誤容忍問題，以及資料平行應用程式在記憶體內的干擾問題。
在現代製程科技中，錯誤的掃描鍊已經可能造成50%的良率損失，我們發
現掃描鍊偵測技術的有效與否不只取決於電路的邏輯依賴且包含了掃描元彼此的控制程度。所以，在本篇論文中，我們提出了一個利用電路架構來分割並重組掃描鍊的方法來增進偵測率。
另一方面，廣域的連結線所造成的延遲已經是效能與耗能的瓶頸所在，3D-IC的出現提供了許多效能以及耗能上的優化。但製造與疊加晶片的過程中可能會因表層粗細不均以及雜質等問題而導致矽穿通道的損壞。許多研究更進一步指出損壞的矽穿通道常會群聚出現。我們針對群聚出現的壞損矽穿通道設計了一簡單又能維持良率的環狀冗餘矽穿通道架構。
在系統層級方面，許多資料平行應用程式會使用共享的記憶體區塊來執行運算，平行的執行緒會在記憶體中體驗到記憶庫衝突，我們設計了一套動態搬移資料區塊的系統架構，可以有效降低記憶體中記憶庫衝突，有效提升系統效能。

With the advances of VLSI design technology, yield loss and performance have become more and more important. To improve the yield of circuits and the performance of systems, we targeted three different problems in circuit level and in system level, which are scan chain diagnosis problem, fault tolerance problem in 3D-ICs, and memory interference problem for data-parallel multi-threaded applications. First, to increase the diagnosis resolution of the scan chains, a scan chain partitioning
algorithm and a scan chain reordering algorithm have been proposed. In modern technology, scan design can be used to detect combinational failures in a circuit and improve the testability of a circuit. However, the defects of scan chains themselves are also critical for the yield loss of the chips. Since scan chains can take up a large portion of the chip area, faulty scan chains can be responsible for up to 50% of yield loss [1]. We observe that the effectiveness of scan chain diagnosis methods depend on not only logic dependency but also the controllability between scan flip-flops. Hence, in this dissertation, we propose a scan chain partitioning algorithm to increase the detectable values of scan cells in the faulty scan chain and a scan chain reordering algorithm to reduce the range of suspect faulty scan cells and to minimize the routing overhead. The experimental results show that our method can reduce the number of suspect scan cells from 378-31 to at most 3 for most cases of ITC’99 benchmarks.

Second, a ring-based redundant TSV architecture is proposed to improve the yield of 3D-ICs. The fabrication and bonding of TSVs may fail because of many factors, such as winding level of the thinned wafers, the surface roughness and cleaness of silicon dies, and bonding technology. In addition, faulty TSVs tend to cluster together because of imperfect bonding technology. To resolve this problem, the router-based redundant TSV architecture was proposed. Their method enables faulty TSVs to be repaired by redundant TSVs that are farther apart. In this dissertation, a new hardware efficient redundant TSV architecture for clustered fault is proposed. Simulation results show that for a given number of TSVs (8 × 8), TSV failure rate (1%), careful selection of grouping ratios, our design achieves 58.9% area reduction of MUXes per signal, 54.6% total area reduction per signal, and 50.54% total wire length reduction while the yield of our ring-based redundant TSV architectures can still maintain 98.47% to 99.00% as compared with router-based design [2]. The minimum shifting length of our ring-based redundant TSV architecture is at most 1 which guarantees the minimum timing overhead of each signal. The maximum extra shifting latency of our ring-based design is reduced 74.7% compared to that of router-based design when the number of faulty TSVs is set to 8.

Finally, a dynamic data migration method to eliminate memory interference of data parallel multi-threaded applications in multi-cores system has been proposed. Data parallelism is a
common parallel programming model that performs operations on a data set which is often regularly structured in an array. In other words, many thread may access the same shared data set. Thus, when the number of threads increases, the probability of memory interference in memory also increases. To address this issue, we provide a new software/hardware cooperative dynamic data migration method by exploiting the update-and-reuse property. Experimental evaluation in a 16-core x86 8-memory banks system shows that our method can improve the system performance by 13.2% compared to traditional OS page coloring method [3] and 9% compared to parallel application memory scheduling method [4].

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