H.264基本規範解碼器在PACDSP雙核心平台上的實作與最佳化

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研究生：	羅健良 Jian-Liang Luo
論文名稱：	H.264基本規範解碼器在PACDSP雙核心平台上的實作與最佳化 The implementation and optimization of H.264 baseline profile decoder on PACDSP dual core platform
指導教授：	石維寬 Wei-Kuan Shih
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	91
中文關鍵詞：	雙核心、解碼、基本規範
外文關鍵詞：	PAC, PACDSP, dual-core, h.264, baseline profile, codec
相關次數：	點閱：2 下載：0
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在今日多媒體充斥的環境下，近一代無線裝置產品都強調本身多媒體的功能。像手機強調一些除了通話本身之外的功能，例如：照相、攝影、播放影片、聽音樂廣播、等等。當然要能夠支援如此豐富的功能也需要相當程度硬體跟軟體的設備來搭配。由於無線裝置的耗電以及執行效能一直是個很重要的議題，所以並不能選擇太高級的硬體來完成如此強大的多媒體功能，但也不能選擇太低接的硬體而導致效能低落而無法執行多媒體的應用。所以在效能以及耗電的考量下，硬體的選擇變成要能更成就一個好的多媒體無線裝置的重要考量的因素。
以目前這些無線裝置來說，雙核心的架構是很受到歡迎的。雙核心指的就是一個MPU(main processor unit)再搭配一個共同的處理器(coprocessor)，而coprocessor有可以分成兩種選擇，一種是DSP，另一種是ASIC。 MPU的部份一般會用來處理一些MMI或是Multi-tasking的工作，而coprocessor的部分一般會用來執行一些運算量比較大且例行的程序。如此的硬體既可以不用選擇高階的處理器也可以執行功能強大的多媒體功能。
本篇論文最主要是在說明在Dual-core的平台架構來實作一個Video Codec的方法與過程以及效能的分析。其中Dual-core的MPU是使用ARM9 20T ，DSP則是採用公研院晶片中心開發的PACDSP，實驗的平台是在工研院的PAC平台上，而Video Code則是採用最近很熱門的H.264/AVC。同時也說明要如何在這樣的架構下如何來實作如此複雜的演算法，以及解釋效能能達到的程度。

In today’s media-rich environment, almost all the new gerenation of wireless device emphasize the functions of one's own multimedia. Liking cell-phone whitch emphasize except some converse functions of itself has the other functions of take pictures, photograph, broadcast the film, listen to the music and broadcast, etc. Certainly must need some degree equipment of hardware and software to support so abundant functions. The power comsumptive and the performance of wireless device has been the very important topic all the time, so can not choose too avdanced hardware to finish so abundant multimedia functions, but also can not choose too low grade hardware to cause efficiency to be low and can not carry out the application of the multimedia. So under efficiency and power comsumptive doing in the test amout, the choice of the hardware is turned into the important topic that can accomplish a good wireless device of multimedia event more.
As to these wireless devices at present, dual-core architecture is popular. Dual-core is referred to that one MPU (main processor unit) matches another common processor (coprocessor), and coprocessor can divide into two kinds of choices, one is DSP, another kind is ASIC. The part of MPU will generally be used for dealing with the work of some MMI or Multi-tasking, and the part of coprocessor will generally be used for carrying out some operation amount bigger and more customary procedures. Hardware like this can needn't choose high-order processor may carry out the powerful multimedia functions too.
Main of this thesis is stating the method, couse and analysis of performance by implementing one Video Codec on Dual-core platform. The MPU in Dual-core choose ARM9 20T , DSP is adopted the PACDSP developed in STC of ITRI, the experimenting platform is in PAC platform of ITRI. And Video Codec has adopted H.264/AVC which is popular very much recently. Also stating how to accomplish such complicated algorithm in such architecture, and how the degree which can reach.

中文摘要    1
Abstract    2
致謝    3
目錄    4
Figure List：    7
Table List：    10
  Introduction    11
1    Background    11
2    Motivation    12
3    Reading Guidance    13
  H.264, System and PACDSP overview    14
1    H.264 Codec    14
1.1    H.264 Structure    14
1.1.1    basic definition    14
1.1.2    Profile    16
1.1.3    Reference Picture    17
1.2    Coded Data Format    18
1.3    Network Abstraction Layer    18
1.3.1    NAL unit    18
1.3.2    VCL and non-VCL NAL units    19
1.3.3    parameter set    20
1.4    Video Coding Layer    20
1.4.1    Encoder and Decoder    20
1.4.2    Macroblock prediction    22
1.4.3    Inter Prediction    22
1.4.3.1    Inter Luma Prediction    23
1.4.3.2    Inter Chroma Prediction    24
1.4.4    Intra Prediction    25
1.4.4.1    Intra Luma Prediction    25
1.4.4.2    Intra Chroma Prediction    29
1.4.5    Transform and Quantization    29
1.4.6    Deblocking Filter    31
1.4.7    Reorder    34
1.4.8    Entropy    34
2    Dual Core System Architecture    35
2.1    System Motherboard Overview    36
2.2    System Architecture    36
3    PAC DSP    37
3.1    PACDSP Architecture    37
3.2    PACDSP Core    38
3.3    Memory Subsystem    38
3.3.1    Instruction Cache    39
3.3.2    Data Memory    39
3.4    PACDSP kernel    40
3.4.1    Program Sequence Control Unit：    40
3.4.2    Scalar Unit：    41
3.4.3    VLIW Data Path：    41
3.5    Cluster Register File Structure    41
3.6    Conditional Execution    43
3.7    Pipeline Architecture    43
  Software Partition and Data structure    46
1    Software Partition    46
2    Data Structure and Memory Allocation    47
3    Data format transform and compact , PreRow data reserve    50
3.1    Data format transform    50
3.2    Data Format Compact    51
3.3    PreRow data reserve    52
4    Program Control Flow and Data Flow    52
4.1    Program Control Flow    52
4.2    Data Flow    54
  Implementation and Optimization    57
1    Inverse Quantization and Inverse Transform + DFT    57
1.1    Luma    57
1.2    Chroma    60
2    Pixel Prediction Compensation + DFC    62
2.1    Impelementation of Intra Prediction    62
2.1.1    Intra Luma 4x4    62
2.1.2    Intra Luma 16x16    66
2.1.3    Intra Chroma 8x8    70
2.2    Impelementation of Inter Prediction    72
2.2.1    Inter Luma 4x4    74
2.2.2    Inter Chroma 2x2    79
2.3    Impelementation of DFC    79
3    Deblocking Filter    80
  Experiment environment and Statistic analysis    82
  Conclusion    87
  Future Work    88
Reference    89
Appendix A    90
A.1 MB data    90
A.2 reference data and prerow data    90
A.3 global parameter and flag    91
Appendix B    92
B.1 BS value in 100 frame of various vedio    92
B.2 motion vector in 100 frame of various vedio    92
B.3 skip mode in 100 frame of various vedio    92

                                

[1] Joint Video Team of ITU-T and ISO/IEC JTC 1, “Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264 | ISO/IEC 14496-10 AVC),” Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVT-G050, March 2003
[2] T. Stockhammer, M. M. Hannuksela, and T. Wiegand, “H.264/AVC in wireless environments” IEEE Trans. Circuits Syst. Video Technol., vol. 13, pp. 657–673, July 2003.
[3] ThomasWiegand, Gary J. Sullivan,Ajay Luthra,Gisle Bj□ntegaard “Overview of the H.264 / AVC Video Coding Standard”
[4] PAC SoC Platform White Paper, December 2004.
[5] “Low Complexity Transform and Quantization – Part I: Basic Implementation” Joint Video Team (JVT) of ISO/IEC MPEG & ITU-T VCEG 2nd Meeting: Geneva, CH, Jan. 29 - Feb. 1, 2002
[6] “Low Complexity Transform and Quantization – Part II: Extensions” Joint Video Team (JVT) of ISO/IEC MPEG & ITU-T VCEG 2nd Meeting: Geneva, CH, Jan. 29 - Feb. 1, 2002
[7] “Full 16-bit implementation of □ pel motion compensation” Joint Video Team (JVT) of ISO/IEC MPEG & ITU-T VCEG 3rd Meeting: Fairfax, Virginia, USA, 6-10 May, 2002
[8] Tiejun Hu, Di Wu “Design of Single Scalar DSP based H.264/AVC Decoder” Link□ping 2005
[9] Shau-Yin Tseng, Ji-Gao Hsu “The profile of H.264” 系統晶片 3 民94.11 頁111-119
[10] Shau-Yin Tseng, Chih-Hao Chang, Tien-Wei Hsieh “Multimedia Programming on PAC SoC Platform” 系統晶片 002期

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