使用取樣分類法的快閃記憶體測試｜國立清華大學博碩士論文庫

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研究生：	董育中 Yu-Chun Dawn
論文名稱：	使用取樣分類法的快閃記憶體測試 Flash Memory Testing Using a Sample Classification Method
指導教授：	吳誠文 Cheng-Wen Wu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	87
中文關鍵詞：	快閃記憶體、測試、取樣、分類、篩選、時間、不確定性、內建自我測試電路
外文關鍵詞：	flash memory, testing, sample, classification, sort, timing, uncertainty, BIST
相關次數：	點閱：2 下載：0
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　　隨著半導體製程持續的進步，以及積體電路設計變得更大型及更快速，不確定性（uncertainty）正成為半導體產業最大的挑戰之一。無法預測的產品行為常常導致低劣的品質及可靠性。因此，對於前瞻性的產品來說，提升晶粒篩選（die sort）精準性的低成本測試技術是非常重要的。
　　目前非揮發性記憶體已經成為半導體產業中成長最快的市場之一，而快閃記憶體（flash memory）則是目前最普遍使用的非揮發性記憶體。然而，大容量、高密度、以及複雜的單元結構使得快閃記憶體的行為難以準確的預測，使其不確定性的問題比起其他積體電路產品更為嚴重。甚至在同一片晶圓裡的晶粒中，因著製程的偏移，不同區域的單元都可能需要不同的測試條件。
　　在這篇論文中，我們提出一個快速、易於使用的取樣分類法。這個方法被應用於快閃記憶體的晶粒篩選、速度篩選、以及運作時間萃取上。此方法不但針對快閃記憶體測試，同時也可應用於面臨同樣問題其他類型的電路。實驗結果證明這個方法有效率且精準的解決了快閃記憶體晶粒挑選的問題。以一個工業界的產品為例，測試時間由8,817大幅的縮短至718毫秒。不僅如此，提出的取樣分類法也適合可測性電路設計。在這個研究中，我們提出一個支援速度篩選及運作時間萃取的內建自我測試電路，可以很容易的被整合於一個單獨的或是內嵌式的記憶體晶片之中。

As the semiconductor process keeps scaling down and IC designs get bigger and faster, uncertainty is becoming one of the greatest challenges for the semiconductor industry. Unexpected and unpredictable behavior of devices often leads to poor quality and reliability. Thus, low-cost test techniques that improve die sorting accuracy are critical for advanced devices.
Nonvolatile memory (NVM) has become one of the most rapidly growing market in the semiconductor industry, and flash memory is currently the most popular NVM. However, large capacity, high density, and a complicated cell structure make flash memory cell behavior difficult to predict
precisely, thus the uncertainty problem is more serious than other IC devices. It can be complicated even when the dies are tested on the same wafer, as cells in different blocks may call for different test conditions due to geometric process variations.
As a fast, easy-to-use solution, we propose a sample classification method. The method is applied to die sort, speed sort, and operation time extraction for diagnosis of flash memory. It is effective not only for flash memory testing, but also for other types of circuits facing similar
test problems. Experimental results show that this method efficiently and accurately solves the flash memory die sort problem . The test time is greatly reduced—from 8,817 ms to 718 ms for an industrial chip. Moreover, the proposed approach is suitable for design-for-testability (DFT)
implementation. In this work, we propose a built-in self-test (BIST) circuit which supports speed sort and operation time extraction, and can easily be integrated with a commodity or embedded memory.

Abstract i
Introduction 1
1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Proposed Method and Target Issue Overview . . . . . . . . . . . . . . . . . . . . 2
3 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Overview of Flash Memory 4
1 Cell Structure and Charge Transfer Mechanism . . . . . . . . . . . . . . . . . . . 5
1.1 Channel Hot Electron Injection (CHEI) . . . . . . . . . . . . . . . . . . . 5
1.2 Fowler-Nordheim (FN) Tunneling . . . . . . . . . . . . . . . . . . . . . . 5
2 Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 NOR Type Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 NAND Type Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Embedded Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Related Testing Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Over-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Program Disturb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Read Disturb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Program/Erase Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Flash Memory Testing 16
1 Test Flow Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1 Die Sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Final Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2 Target Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1 Custom Test Parameters in Die Sort Stage . . . . . . . . . . . . . . . . . . 18
2.2 Speed Sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 Precision of the Threshold Voltages . . . . . . . . . . . . . . . . . . . . . 20
Sample Classification Method 22
1 Sample Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2 Sample Classification with Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . 25
3 Error Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Testing Using Sample Classification 29
1 Die Sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.1 Previous Method: Scan (Ramp) Test . . . . . . . . . . . . . . . . . . . . . 29
1.2 Proposed Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2 Speed Sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.1 Timing Sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2 Speed Sort Test Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3 Operation Time Extraction for Diagnosis . . . . . . . . . . . . . . . . . . . . . . . 33
3.1 Stress Time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2 Operation Time Extraction Flow . . . . . . . . . . . . . . . . . . . . . . . 35
Design of Built-In Self-Test Circuit 39
1 Target Memory Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2 A Built-In Self-Test Circuit with Sample Classification Function . . . . . . . . . . 41
2.1 Extra Hardware for Sample Classification . . . . . . . . . . . . . . . . . . 41
2.2 Speed Consideration for Read Speed Sorting . . . . . . . . . . . . . . . . 42
3 Proposed BIST Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2 I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3 Test Command/Result Format . . . . . . . . . . . . . . . . . . . . . . . . 45
4 Proposed BIST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.1 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2 Test Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Experimental Results 59
1 Die Sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Conclusion and Future Work 63
1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

                                

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