因單電子電晶體在室溫下極低功耗的表現，因此已被當作有潛力拓展摩爾定律(Moore's law)的硬體。之前已有許多研究提出在單電子電晶體陣列上實作布林函式(Boolean function)的映射方法。然而，這些方法皆建立於一理想的假設，即單電子電晶體不會發生缺陷。近來，有一套針對有缺陷之單電子電晶體的診斷方法被提出。然而，此方法為靜態因此其表現上缺乏效率。因此，在此論文中，我們提出一套動態診斷方法以有效率的方式辨別單電子電晶體陣列上缺陷的位置與類型。實驗結果顯示提出的動態診斷方法可以花費較少的執行時間而達到與靜態診斷方法相同之結果。此外，在幾組實驗中，我們提出的方法可以在數秒之內完成，而靜態診斷方法則無法在三千六百秒內完成。

Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending the Moore’s law due to its ultra low power consumption. Previous works proposed mapping approaches to implement Boolean functions on SET arrays. However, these approaches were based on an ideal assumption that the SET arrays are defect-free. Recently, a diagnosis method was proposed targeting at defective SET arrays. However, the approach was static such that the performance is inefficient. As a result, in this paper, we propose a dynamic diagnosis approach that can efficiently identify the locations and the types of the defects in the SET arrays. The experimental results show that the proposed dynamic diagnosis approach can achieve the same results as the previous work with much less CPU time on a set of benchmarks. Furthermore, the proposed method spent a few seconds while the previous work exceeded the CPU time limit of 3600 seconds on the some benchmarks.

[1] N. Asahi, M. Akazawa, and Y. Amemiya, “Single-Electron Logic Device
Based on the Binary Decision Diagram,” IEEE Trans. Electron Devices,
vol. 44, pp. 1109-1116. 1997.
[2] Y.-C. Chen, S. Eachempati, C.-Y. Wang, S. Datta, Y. Xie, and V.
Narayanan, “Automated Mapping for Reconfigurable Single-Electron
Transistor Arrays,” in Proc. Design Automation Conf., pp. 878-883,
2011.
[3] Y.-C. Chen, S. Eachempati, C.-Y. Wang, S. Datta, Y. Xie, and V.
Narayanan, “A Synthesis Algorithm for Reconfigurable Single-Electron
Transistor Arrays,” ACM Journal on Emerging Technologies in Computing
System, Vol. 9, No. 1, Article 5, February 2013.
[4] Y.-H. Chen, J.-Y. Chen, and J.-D. Huang, “Area Minimization Synthesis
for Reconfigurable Single-Electron Transistor Arrays with Fabrication
Constraints,” in Proc. Design, Automation and Test in Europe, pp. 1-4,
2014.
[5] Y.-H. Chen, Y. Chen, and J.-D. Huang, “ROBDD-based Area Minimization
Synthesis for Reconfigurable Single-Electron Transistor Arrays,” in
Proc. Int. Symp. on VLSI Design, Automation and Test, pp. 1-4, 2015.
[6] C.-E. Chiang, L.-F. Tang, C.-Y. Wang, C.-Y. Huang, Y.-C. Chen, S.
Datta, and V. Narayanan, “On Reconfigurable Single-Electron Transistor
Arrays Synthesis Using Reordering Techniques,” in Proc. Design,
Automation and Test in Europe, pp. 1807-1812, 2013.
[7] S. Eachempati, V. Saripalli, V. Narayanan, and S. Datta, “Reconfigurable
Bdd-based Quantum Circuits,” in Proc. Int. Symp. on Nanoscale Architectures,
pp. 61-67, 2008.
[8] H. Hasegawa and S. Kasai, “Hexagonal Binary Decision Diagram Quantum
Logic Circuits Using Schottky In-Plane and Wrap Gate Control of
GaAs and InGaAs Nanowires,” Physica E: Low-dimensional Systems
and Nanostructures, vol. 11, pp. 149-154, 2001.
[9] S.-Y. Huang and K.-T. Cheng, “ErrorTracer: A Fault Simulation Based
Approach to Design Error Diagnosis,” IEEE Trans. on Computer-Aided
Design, pp. 1341-1352, 1999.
[10] C.-Y. Huang, C.-W Liu, C.-Y. Wang, Y.-C. Chen, S. Datta and V.
Narayanan, “A Defect-aware Approach for Mapping Reconfigurable
Single-Electron Transistor Arrays,” in Proc. Asia and South Pacific
Design Automation Conf., pp. 118-123, 2015.
[11] C.-Y. Huang, Y.-J Li, C.-W Liu, C.-Y. Wang, Y.-C. Chen, S. Datta and
V. Narayanan, “Diagnosis and Synthesis for Defective Reconfigurable
Single-Electron Transistor Arrays,” IEEE Trans. VLSI Systems, 2016.
[12] S. Kasai, M. Yumoto, and H. Hasegawa, “Fabrication of GaAs-based
Integrated 2-bit Half and Full Adders by Novel Hexagonal BDD Quantum
Circuit Approach,” in Proc. Int. Symp. on Semiconductor Device
Research, pp. 622-625, 2001.
[13] W. H. Kautz, “Fault testing and diagnosis in combinational digital
circuits,” IEEE Trans. Computers, vol. C-17, pp. 352-366, 1968.
[14] H.-T. Liaw, J.-H. Tsaih, and C.-S. Lin, “Efficient automatic diagnosis of
digital circuits,” in Proc. IEEE Int. Conf. Computer-Aided Design, pp.
464-467, 1990.
[15] C.-W. Liu, C.-E. Chiang, C.-Y. Huang, C.-Y. Wang, Y.-C. Chen, S.
Datta, and V. Narayanan, “Width Minimization in the Single-Electron
Transistor Array Synthesis,” in Proc. Design, Automation and Test in
Europe, 2014.
[16] C.-W. Liu, C.-E. Chiang, C.-Y. Huang, C.-Y. Wang, Y.-C. Chen, S. Datta,
and V. Narayanan, “Synthesis for Width Minimization in the Single-
Electron Transistor Array,” IEEE Trans. VLSI Systems, pp. 2862-2875,
2015.
[17] L. Liu, X. Li, V. Narayanan and S. Datta, “A Reconfigurable Low-
Power BDD Logic Architecture Using Ferroelectric Single-Electron
Transistors,” IEEE Trans. Electron Devices, vol. 62, no. 3, pp. 1052-
1057, 2015.
[18] H. W. Ch. Postma, T. Teepen, Z. Yao, M. Grifoni, and C. Dekker,
“Carbon Nanotube Single-Electron Transistors at Room Temperature,”
Science, vol. 293, pp. 76-79, 2001.
[19] Y. T. Tan, T. Kamiya, Z. A. K. Durrani, and H. Ahmed, “Room Temperature
Nanocrystalline Silicon Single-Electron Transistors,” Journal of
Applied Physics, vol. 94, pp. 633-637, 2003.
[20] A.Veneris and I. N. Hajj, “Design error diagnosis and correction via
test vector simulation,” IEEE Trans. Computer-Aided Design, vol. 18,
no. 12, pp. 1803-1816, 1999.
[21] Z. Zhao, C.-W. Liu, C.-Y. Wang, and W. Qian, “BDD-Based Synthesis
of Reconfigurable Single-Electron Transistor Array,” in Proc. Int. Conf.
on Computer-Aided Design, pp. 47-54, 2014.
[22] L. Zhuang, L. Guo, and S. Y. Chou, “Silicon Single-Electron Quantum-
Dot Transistor Switch Operating at Room Temperature,” Applied Physics
Letters, pp. 1205-1207, 1998.