在本論文中，我們探討了現有建構低密度同位元 (Low-Density Parity-Check)編解碼的方式應用在非揮發性記憶體上。在現有的規格之下，基於面積以及處理效能的考量我們使用了旋轉矩陣來建構LDPC的編解碼。我們建構了一套模擬系統針對於整個編解碼流程以及各種不同旋轉矩陣的的碼率 (code rate)用以觀察其更正能力以及比較其他種類的錯誤更正碼 (BCH code)。在經過分析探討LDPC解碼的演算法後，我們決定採用佈於對數值域的SPA (sum-product algorithm)。在硬體實作上我們則是用LBPA (Layered Belief Propagation Algorithm)由SPA改進。在對數值域之下，所有運算都是整數運算可以簡化硬體設計的處理。

關於LDPC編解碼硬體架構，面積是很有效率的被使用。由於採用的旋轉矩陣建構LDPC，這使得整個架構可以延伸到不同的碼率以針對不同的應用，並且架構裡平行的運算單元可以輕易提升處理效能。除此之外我們提出了一個相當有效的壓縮記憶體使用方式並且解壓縮後無損其更正能力。最後我們實作了一個LDPC邊解碼的硬體設計針對於現有記憶體規格。

對於未來的展望，我們可以考慮將LDPC跟BCH這兩種錯誤更正碼合併可以讓這樣組合的碼率更有更正能力。並且找尋更有更正能力的LDPC邊解碼方式以及改善硬體的架構已針對非揮發性記憶體以及固態硬碟等等之應用。

In this thesis, we evaluated the existing technologies of LDPC (low-density parity check)
codes for the error correcting scheme of the non-volatile memories. With the consideration
of the cost-effectiveness, the ¼-matrix approach has been adopted for the parity-check matrix.
The system model was constructed to evaluate the performance and encoding/decoding behavior
of our LDPC CODEC (Encoder/Decoder) with various code rates. After the analysis
of coding performance, we used sum-product algorithm in logarithm domain as the decoding
approach, and adopted the layered belief propagation algorithm. In addition, the decoding
indexes are implemented with integer numbers to simplify the hardware.
The overall LDPC CODEC is area efficient. The scalable architecture makes our CODEC
suitable for a large variety of code rates. Parallel architecture can be easily implemented
to speed up the throughput. In addition, the memory usage is dramatically reduced in our
design without affecting the correcting performance. A design for the modern flash memory
has been implemented to validate our LDPC CODEC.
Our future works includes the study and design of the hybrid BCH and LDPC codes to
further increase the effective code rate, also the searching of the more efficient LDPC codes,
and the improvement of the encoding/decoding architecture, with the consideration of the
future non-volatile memories and solid-state disks.

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