近年來在3D 顯示器上已經有廣泛的研究，而我們也對3D 顯示器在未來市
場的潛力抱有期望，因此我們致力於一種稱為光場顯示器的3D 顯示器，因為
它將較於同種顯示器有著高解析度和全視差的優勢。在光場顯示器上，我們使
用雙層液晶螢幕的架構搭配一個稱為光場分解的技術，而在光場分解這項技術
上，我們採用一種稱為非負整數矩陣分解的疊代演算法。然而這個演算法需要
很高的運算量，有其他研究提出利用圖形處理器來對這個演算法加速，但依然
無法滿足我們對於即時全高清規格的應用，所以在這篇論文中，我們將這個計
算繁重的非負整數矩陣分解實現到特殊應用積體電路，而透過我們的數位晶片
可以做到即時全高清的光場分解。
我們將非負整數矩陣分解這個演算法在硬體實現上的問題分成兩部分，第一
部分為應用於光場分解的定點數非負整數矩陣分解，第二部分為非負整數矩陣
分解引擎的系統架構。應用於光場分解的定點數非負整數矩陣分解過去沒有人
討論過，所以我們會討論我們定點數非負整數矩陣分解的作法，包含定點數除
法和內部量化。在整個運算之中，除法在硬體實現上是最關鍵的部分，考慮到
硬體上的表現，我們為了光場分解設計了除法，且這個除法運用到傳統倒數查
表的作法，而基於相同的原因，我們也根據光場還原的品質對內部的運算做量
化來降低硬體複雜度，相較於原本保留完整精確度的作法，我們的實作可以提
升34% 的面積延遲乘積。第二部分是為了高通量的光場分解所設計的非負整數
矩陣分解引擎系統架構，在這個系統當中，我們用了多組乘法更新單元來執行
定點數非負矩陣分解，為了最大化我們引擎的硬體效率，我們提出了一個分解
控制設計，這個設計相較於直接的設計可以減少68% 的運算時間。
我們為了光場顯示器實現了一個使用台積電四零奈米半導體製程的超大型積
體電路來支援即時全高清的光場分解，在這篇論文中我們提出了一個非負整數
矩陣分解引擎，這個引擎使用了630 萬個邏輯閘，且當運行在200 MHz 的頻率
下，它可以提供每秒36G 個像素的吞吐量，而功耗的部分我們透過寄生電容在
時間上的功耗來估計，結果為1.07 瓦。

3D displays have been widely studied in recent years, and we are optimistic about their potentiality in the future market as well. Thus, we target one of the 3D displays called light field display due to its high resolution and full parallax. We adopt the architecture of dual-layer LCDs with the technique called light field factorization. We exploit the iteration-based algorithm Non-negative Maxtrix Factorization(NMF) to implement light field factorization. However, this algorithm needs high computation. The acceleration with GPU in other works is not sufficient for our real-time Full HD application. In this thesis, we implement this time-consuming algorithm ---Non-negative Matrix Factorization--- into ASIC. Using our VLSI architecture can achieve the throughput of real-time Full HD for light field factorization.
The issues of our hardware implementation on NMF are divided into two parts: fixed-point NMF for light field factorization and system architecture of NMF engine. Fixed-point NMF applied on light field factorization has not been discussed before. Therefore, we will introduce our fixed-point NMF implementation including fixed-point division and internal quantization. In the overall computation, the division operator is the most critical part for hardware implementation. For the consideration of hardware performance, we design the division for light field factorization with the conventional reciprocal look-up table division. For the same purpose, we quantize the internal operation bitwidth according to the light field reconstruction quality to reduce the hardware complexity. Comparing to the full precision implementation, our implementation can enhance 34% of the area-delay product. The second issue is the system architecture of our NMF engine for high-throughput light field factorization. In the system, we have multiple multiplicative update units performing the fixed-point NMF computation. To maximize the hardware efficiency of our engine, we proposed a factorization control scheme. With this control scheme, our NMF engine can reduce 68% of computing time compared to a direct scheme.
We implemented a VLSI circuit to support real-time Full HD light field factorization for light field display using TSMC 40 nm technology process. Our proposed design called NMF engine is given in this thesis, which costs 6.3M logic gates.
It can provide 36G pixel/sec of throughput when operating at 200 MHz. The power consumption is 1.07 W which is measured using time-based power estimation with extracted parasitics.

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