The continuing trend to embed more on-chip test circuits results in an increasing complexity, which requires more efforts on design and validation. Design and simulation at system level are more and more important. In this thesis, we use a wireless test system as an example, to demonstrate the efficiency of system-level techniques in assisting circuit specification exploration, with the goal of area and test-cost reduction. We model the wireless test system in SystemC by using transaction-level modeling methodology which can give high level of abstraction and improve the simulation efficiency. In addition, we define a set of communication API and library which help designers
implement test program. We also introduce a circuit-under-test (CUT) modeling method that can evaluate our model, which acts as a virtual tester. In our experiments, we parameterize several design variables such as buffer size, error-checking bit size, etc., and perform the search method to find the optimal design specifications based on different test conditions, such as different amount of
test results, different parallelism, etc., on Memory BISTs. We find that the optimal combinations of design specifications can reduce cost (including test and chip area) by 10% to 40%, in comparison with original ad-hoc design.

　　隨著將測試電路內嵌在晶片上成為趨勢，電路複雜度持續增加，也導致在設計或驗證上需要更多心力。因此，系統層級的設計和模擬益加重要。在這篇論文中，我們以無線測試系統當作例子，展現利用屬於系統層級 (electronic system level) 的技巧，在以同時減少晶片面積成本和測試時間成本為目標下，有效率地協助制定設計規格。藉由 SystemC 語言中轉換層級模型 (transaction-level modeling) 建構方法，可以提高我們無線測試平台模型抽象層級和模擬效率。除此之外，我們訂定一套溝通應用程序介面 (application programming interface) 和函式庫 (library) ，幫助設計者開發適用於無線測試系統的測試程式。我們同時提出一種待測電路模型建置方法，可用來評估被視為虛擬測試平台的無線系統模型。在實驗中，藉由搜尋方法以及調整不同的設計參數，例如緩衝區大小、錯誤檢查碼多寡等，在不同的測試環境中尋找最適當的無線測試系統設計規格。這些不同的測試環境，包括測試結果多寡、平行化數量等。從實驗結果中可以發現，最佳的設計規格組合相較於原先直覺設計下的設計規格組合，可以減少包含測試時間成本及晶片面積成本達10%到40%。

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