本論文提出一新型p通道內嵌式無閘極記憶胞結構，此記憶胞優點包括：製程歩驟簡易，完全和先進的90奈米CMOS邏輯製程技術相容，具有比傳統One-Time Programming(OTP)還快的元件編程與讀取能力，低功率消耗特性，以及可紫外光抹除此P通道內嵌式無閘極記憶胞之儲存點是建立在一寄生的ONO結構，ONO結構由氧化層(Resistor-Protection-Oxide，簡稱RPO)，接觸蝕刻停止層(Contact Etching Stop Layer，簡稱CESL)，和內部間介電層(Inter Level Dielectric，簡稱ILD)組成。無閘極記憶胞包含一無閘極儲存點，與一選擇電晶體，適合NOR陣列操作。此新提出之記憶胞的編程操作機制是使用通道熱電洞引發熱電子注入，利用紫外光照射完成抹除操作。本論文同時利用二維製程及元件模擬器進行元件特性驗證。經量測結果證明，所提出之新型p通道內嵌式無閘極記憶胞相較於傳統OTP記憶體有相當大的改進及製作成本上的優勢，可廣泛應用在內嵌式的非揮發性記憶體上。

A novel p-channel gateless one-time programming cell is proposed. Its advantages include full compatibility with advanced CMOS logic technology, fast programming and read operations, and low power dissipation. This UV-erasable, p-type gateless storage node is based on a parasitic ONO structure comprised by Resistor-Protection-Oxide (RPO), Contact Etching Stop Layer (CESL), and Inter level Dielectric (ILD). The proposed cell contains a gateless storage node and a select transistor, and can be easily arranged into a NOR-type array. The operation mechanisms of the new proposed cell are channel hot hole induced hot electron injection (CHHIHE) for programming and ultraviolet (UV) exposure for erasing. 2D process and device simulation is also employed in this essay to provide insight to operation mechanisms of this cell, and reveal the first-hand device characteristics, determine the operation condition. The novel p-channel embedded gateless cell are demonstrate in 90nm CMOS technology in this study. The measurement results shows advantageous performance in fabrication cost and scalability than the transitional One-time Programmable memory, and suggest that this novel device is widely suitable for embedded nonvolatile memory application in advanced logic technologies.

[1] C. Kothandaraman , S.K. Iyer, S.S. Iyer, "Electrically Programmable Fuse (eFUSE) Using Electromigration in Silicides", IEEE Electron Device Letters, vol. 23, no. 9, pp.523-525, 2002.
[2] J. Peng, G .Rosendale, M. Fliesler, D. Fong, J. Wang, C. Ng, Zs Liu, Harry Luan, " A Novel Embedded OTP NVM Using Standard Foundry CMOS Logic Technology", IEEE, 2006.
[3] M. Chi and A. Bergemont, "A new single-poly Flash Memory Cell with low-voltage and low-power operations for embedded applications", Device Research Conference Digest, 5th, pp. 126-127, 1997.
[4] Ching-Yuan Lin, Chung-Hung Lin, Chien-Hung Ho, Wei-Wu Liao, Shu-Yueh Lee, Ming-Chou Ho, Shih-Chen Wang, Shih-Chan Huang, Yuan-Tai Lin and Charles Ching-Hsiang Hsu, "Embedded OTP Fuse in CMOS Logic Process" ,IEEE, 2005.
[5] Ching-Sung Yang, Shih-Jye Shen, and Ching-Hsiang Hsu, "Single Poly UV-Erasable Programmable Read Only Memory", US Patent # US 6,882,574 B2, Apr.19, 2005.
[6] C.C.-H. Hsu, A . Acovic, L. Dori, B. Wu, T. Lii, D. Quinlan , D. DiMaria, Y. Taur, M. Wordeman and T. Ning, "A High Speed, Low Power P-Channel Flash EEPROM Using Silicon Rich Oxide as Tunneling Dielectric", in Ext. Abstract of 1992 SSDM, pp.140, 1992.
[7] Ching-Sung Yang, Shih-Jye Shen, and Ching-Hsiang Hsu, "Single Poly Embedded EPROM", US Patent #US 6,885,587 B2, Apr.26, 2005.
[8] Ching-Hsiang Hsu, Chih-Hsun Chu, Ming-Chou Ho, and Shih-Jye Shen, "Method For Forming EPROM With Low Leakage", US Patent # US 6,740,556 B1, May 25, 2004.
[9] Robert S.C. Wang, Rick S.J. Shen and Charles C. H. Hsu," Neobit-High Reliable Logic Non-Volatile Memory (NVM)", IEEE, 2004.
[10] H. A. R. Wegener, A .J .Lincoln, "The variable threshold transistor, A new electrically alterable, non-destructive read-only storage device", IEDM Tech. Dig., Oct. 1967.
[11] James D. Plummer, Michael D. Deal, Peter B. Griffin, "Silicon VLSI Technology", pp. 542.
[12] Roy S. Bass, "Non-Volatile Memory Cell Having Si Rich Silicon Nitride Charge Trapping Layer", US Patent#4,870,470, 1989.