摘要

本篇論文提出一新穎鈷化矽熔絲元件，此元件已驗證於 0.18μm 標準邏輯製程。
此記憶元件可內嵌於一般 CMOS 標準邏輯製程，不需作光罩的更動，利用電子遷移的原理使矽化物中斷，達成單次寫入的目的。此篇論文特殊的地方是利用 RPO 去定義出狹窄的矽化物形狀，以此方法可降低寫入電流達 4.4mA，比對照組少了20%的電流，缺點是寫入電壓達 5V，對於先進邏輯來說此寫入電壓偏高。
為了解決此問題，兩種結構被提出，經由模擬的結果，此兩種結構可有效地降低寫入電壓，達成在先進邏輯中存取的目的。

Abstract

In this study, a novel logic OTP cell using offset define silicide structure was demonstrated. The silicon data has proven that this cell can be adapted in 0.18 μm technology node.

The ODS fuse is compatible with logic CMOS process without additional change in masks. Electromigration/ rupture is used as the program mechanism for the ODS fuses. The unique design feature in this cell is to utilize RPO to define narrow silicide portion and realize low program current target. This cell can achieve 4.4mA program current which is 20% reduction from the reference symmetrical fuse. However, program voltage of 5V is too high for advance circuits.

To compensate this issue, two alternative structures are proposed. These two solutions retain the idea of offset define while successfully suppressing the program voltage. They have not been silicon verified, but simulation shows the program voltage can be effectively reduced to meet the need for fuses embedded in advanced logic circuits.

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