在新一代的行動通訊系統中採用了所謂正交分頻多工擷取 ( OFDMA )的技術。在一個OFDMA的系統中，次載波被分成多個resource block且分配給多個使用者使用，對於使用者來說只會使用到一個OFDM symbol中的部份次載波，為了達到低功率的需求，不再需要原先完整的快速傅立葉轉換 (FFT) 運算，假如能根據resource block的使用方式，只運算實際所需運算的部份，則將能有效率地減少功率的消耗與運算的時間。在本論文中，我們提出一套能根據不同resource block的使用方式，控制cached-FFT 處理器，只運算需要運算的部份。藉著推出的partial cached-FFT演算法，我們設計了一個支援128點到1024點的partial cached-FFT 處理器。另外，twiddle factor乘法器佔了全部butterfly運算中很大的運算比例，所以為了降低功率的消耗，設計了一個能根據FFT運算中信號的動態範圍和使用之不同constellation做調整之功率可感知的乘法器。最後，根據cell-based 設計流程，我們使用tsmc 0.18um cell library去進行晶片實做。根據我們設計的處理器，我們最多可以降低功率消耗到原先完整FFT運算的36.36％。

Orthogonal frequency division multiplex access (OFDMA) is employed in the next-generation mobile communication systems. In OFDMA system, subcarriers can be grouped as several resource blocks and allocated to different users. So partial subcarriers of one OFDM symbol are used by one user and full FFT computation is unnecessary for low-power requirement. If we can only compute the required part of full FFT computation in terms of allocated resource blocks, the power consumption and processing time can be saved efficiently. In this thesis, we propose a partial cached-FFT algorithm on cached-memory architecture to control the operation of cached-FFT architecture in terms of allocated resource blocks. By proposed partial cached-FFT algorithm, we design a variable-length partial cached-FFT processor from 128-point to 1024-point. In addition, twiddle factor multiplier is computationally intensive element of one butterfly operation. So the power-aware multiplier is designed in terms of signal dynamic range in FFT computation and different constellation in order to reduce power consumption. Finally, we use the cell-based design flow to implement proposed design with TSMC 0.18um cell library. By the proposed processor, we can reduce power consumption to 36.34% of full FFT computation at most.

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