可程式化邏輯閘陣列加速之期貨市場隱含波動率計算器

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研究生：	李宇凡 Lee, Yu-Fan
論文名稱：	可程式化邏輯閘陣列加速之期貨市場隱含波動率計算器 An FPGA-Accelerated Implied Volatility Calculator for Futures Market
指導教授：	馬席彬 Ma, Hsi-Pin
口試委員:	蔡佩芸 Tsai, Pei-Yun 黃元豪 Huang, Yuan-Hao
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2022
畢業學年度：	110
語文別：	英文
論文頁數：	64
中文關鍵詞：	高頻交易、硬體加速、高階合成、可程式化邏輯閘陣列、隱含波動率
外文關鍵詞：	High-Frequency Trading, Hardware Acceleration, High-level Synthesis, FPGA, Implied Volatility
相關次數：	點閱：2 下載：0
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查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

隱含波動率是在金融市場中一個重要的指標，用於判斷市場行情的趨勢。因此透過減少計算的延遲，可以幫助使用者掌握實際金融市場的狀況。在這篇論文中，我們設計了用高階合成的方式，加速我們開發模組功能的過程，也能夠與使用基於場效可程式化邏輯閘陣列的高頻交易系統結合使用。
設計時使用了變數變換，減少重複計算的次數。並且改良傳統的二分法，發揮場效可程式化邏輯閘陣列平行運算的優勢，一次計算一百組布萊克-休斯模型，加速收斂逼近的結果。使用浮點數常數儲存，避免浪費過多的計算時間。最後則針對累積正態分布函數化簡，透過誤差函數表示，並使用漸進展開的方式進行逼近。
本篇論文針對此模組功能進行硬體測試，使用臺灣證券交易所股價指數期貨當作測試資料來驗證此模組。經實驗結果得到和軟體程式計算的結果一致，除此之外，執行在場效可程式化邏輯閘陣列上計算的延遲約為600奈秒，而計算結果與真實情況的均方誤差約為5.76*10^(-6)，平均絕對誤差約為2.23*10^(-3)。

Implied volatility is an essential indicator in financial markets to determine the trend of the market. Therefore, reducing the delay in the calculation helps the user understand the actual financial market conditions. In this thesis, we use the method of high-level synthesis to speed up developing our module functions. It can also combine with the high-frequency trading system on field-programmable gate array (FPGA).

The design uses variable transformations to reduce the number of iterations. We also improve the traditional bisection method to take advantage of the FPGA parallel computation and compute 99 sets of Black-Scholes model at a time to accelerate the convergence approximation results. We store the floating-point constants to avoid wasting too much computation time. Finally, the cumulative normal distribution is simplified through an error function and approximated with asymptotic expansion.

This thesis conducts a hardware test on the module function and uses the Taiwan Index Futures as the test data to verify the module. The results are consistent with the results calculated by the software program. In addition, the delay of the calculation on FPGA is about 600 ns. The mean squared error (MSE) of the calculation results is about 5.76*10^(-6) and the mean absolute error (MAE) is about 2.23*10^(-3).

Abstract i

Introduction 1
1 Background . . . . . . . . . . . . . . . . . . . 1
2 Motivation . . . . . . . . . . . . . . . . . . . . 2
3 Main Contributions . . . . . . . . . . . . . . 3
4 Organization . . . . . . . . . . . . . . . . . . . . 3

Background Knowledge and Literature Survey 5
1 Black-Scholes Model . . . . . . . . . . . . . . . . . . . 5
1.1 Development and Fundamental Hypotheses . . . . . . . . . . . . . . 5
1.2 Black-Scholes Formula and the Implied Volatility . . . . . . . . . . . 6
2 Related Works . . . . . . . . . . . . . . . . . . . . 8
2.1 Closed-form Method . . . . . . . . . . . . . . . . . . . 8
2.2 Numerical Method . . . . . . . . . . . . . . . . . . . . 17
2.3 Hardware Acceleration . . . . . . . . . . . . . . . . . . . . 18
3 Vivado High-level Synthesis . . . . . . . . . . . . . . . . . . . . 20
3.1 Development and Evolution . . . . . . . . . . . . . . . . . . . . 20
3.2 Design Flow . . . . . . . . . . . . . . . . . . . . 22
3.3 Coding Style . . . . . . . . . . . . . . . . . . . . 25

Proposed Modified Model 27
1 Finding Implied Volatility System . . . . . . . . . . . . . . . . . . . . 27
1.1 Variable Transformation . . . . . . . . . . . . . . . . . . . . 29
1.2 Unrolled Calculation . . . . . . . . . . . . . . . . . . . . 32
1.3 Floating-point Constant Storage . . . . . . . . . . . . . . . . . . . . 37
1.4 Approach of Normal Cumulative Distribution Function with Erf() . . 38
2 Vivado IP Introduction . . . . . . . . . . . . . . . . . . . . 41
2.1 Xilinx DMA/Bridge Subsystem for PCI Express . . . . . . . . . . . 41
2.2 Clocking Wizard . . . . . . . . . . . . . . . . . . . . 42
2.3 FIFO Generator . . . . . . . . . . . . . . . . . . . . 44

Implementation Results 47
1 Device and Test Environment . . . . . . . . . . . . . . . . . . . . 47
2 Utilization of Hardware . . . . . . . . . . . . . . . . . . . . 49
3 Experimental Results . . . . . . . . . . . . . . . . . . . . 49
Conclusion and Future Works 59
1 Conclusion . . . . . . . . . . . . . . . . . . . . 59
2 Future Works . . . . . . . . . . . . . . . . . . . . 60

Bibliography 61
                                

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