研究生: |
康家榕 Kang, Chia-Jung |
---|---|
論文名稱: |
運用Fuzzy C-means與均勻化法解決半導體化學機械研磨平坦化問題 Using Fuzzy C-means and Homogenization to Solve the Uniformity Problem of the Chemical Mechanical Polishing Process in Semiconductor Manufacturing |
指導教授: |
陳飛龍
Chen, Fei-Long 劉淑範 Liu, Shu-Fan |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 工業工程與工程管理學系 Department of Industrial Engineering and Engineering Management |
論文出版年: | 2010 |
畢業學年度: | 98 |
語文別: | 中文 |
論文頁數: | 80 |
中文關鍵詞: | 化學機械研磨 、淺碟效應 、虛擬電路 、Fuzzy C-means 、均勻化法 |
外文關鍵詞: | Chemical mechanical polishing, Dishing, Dummy feature, Fuzzy C-means, Homogenization |
相關次數: | 點閱:2 下載:0 |
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半導體產業具有高成本與低生命週期的特性,如何提升良率減少不良品產生,進而使得企業獲利提升是一項重要的課題。在半導體生產總成本中,研發設計階段影響了百分之九十五的成本,故若能在該階段即找出影響良率的因子,則將會更有效的提升良率。由於晶圓製造之層級多又複雜,在進行薄膜製程時晶圓表面會形成高低不平的沉積現象,對於下一步驟的微影製程將會產生對焦上的問題影響晶圓製造的良率,而利用化學機械研磨法能即時改善此問題,進而使晶圓表面達到全面性的平坦化,但若晶圓片本身密度不均,則研磨墊加之於在晶圓表面的應力不一致,造成晶圓表面凹陷此現象則為所謂的淺碟效應,為了使晶圓表面電路密度均勻化,其主要採用的改善方式是在不改變原有電路設計的前提下,在較低電路密度的區域填入虛擬電路。因此,本研究的目的為找出一個有效率且快速的方法來對一電路設計圖填充虛擬電路,使整個晶圓表面電路平坦化,本研究之方法首先針對晶圓電路圖資料衡量其電路密度,為了降低龐大資料的複雜度,以Fuzzy C-means法來做群集分析將密度接近的區塊分為一群,最後利用本研究提出之均勻化法針對密度較低的區塊予以填入虛擬電路並分析結果。本研究結果顯示透過所提出之研究方法在分析處理時間1分鐘內及不同的參數設定下,分別可將電路密度標準差降低49%與69%,有效的降低電路密度的變異使電路表面平坦化。
Semiconductor fabrication has the characteristics of short manufacture’s life cycle and high production costs. It is therefore considerably important to boost the production yield rate in order for the enterprises to profit. Among manufacturing costs, 95% is affected by design, thus the earlier one finds the influence the better. Integrated circuits(IC)are composed of many overlapping layers, thus irregular topography will leave the surface of ICs during fabrication. Chemical mechanical polishing(CMP)removes material and tends to even out any irregular topography, making the wafer planar; this is necessary in order to bring the entire surface within the depth of field of a photolithography system. The most significant problem arises when polishing is “dishing”, which is a form of local planarization where areas of the wafer are polished faster than others. To solve this problem, the common practice is to design dummy feature into the dies such that the variability of the circuit density can be reduced and the dishing problem can be eliminated. This research focuses on efficient dummy feature placement. First, simulate the IC’s data map. Second, calculate the density of the simulated data. Third, use fuzzy C-means to cluster the data with similar density into the same group for lowering the complexity of huge databases. And finally, place dummy feature into low circuit density data groups by self-generated homogenization methods and then analysis the results. The calculation can come from the results in less than 1 minute and lower the variability of density by 49% and 69% respectively via different parameter settings which fulfill the research purpose.
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