摘要
隨著可攜式電子產品的蓬勃發展，內嵌式非揮發性記憶體的市場需求量大增，內嵌式非揮發性記憶體的開發逐漸受大家重視，其中，單一複晶矽浮動閘極非揮發性記憶體成為目前市場的主流，然而，目前已發展的單一複晶矽閘極非揮發性記憶體大多有著元件浮動閘極耦合率過低，導致在元件操作上受到許多限制。本論文提出一新型N通道接點耦合閘極多次寫入非揮發性記憶體，在標準邏輯製程下，藉由耦合接點結構來提升元件對浮動閘極的耦合能力。
新型N通道接點耦合閘極多次寫入非揮發性記憶體採用單一複晶矽閘極架構，寫入操作以通道熱載子轟擊引發熱電子注入，與利用Fowler-Nordheim穿遂效應進行抹除操作，可以多次性寫入與抹除。此新型元件可在50ms內完成寫入操作，抹除時間則為150ms，再者元件的耐久度可達10K次，資料保存性在125oC下達1000小時以上的考驗。基於耦合接點的特性，此元件不需額外的耦合井即可進行電性抹除，在陣列運用上也不需要額外的選擇閘極，因此有著極小的細胞尺寸，很適合應用於高密度的記憶體陣列。此新型元件擁有良好的操作特性與資料可靠度，與極小的細胞尺寸，提供內嵌式非揮發性記憶體一個新的選擇與應用。

bedded nonvolatile memory (eNVM) are growing fast, and single poly floating gate eNVM is the mainstream in the market. However, single poly floating gate eNVM has faced the challenge that the coupling ratio of the floating gate is too small, result in the difficulties in cell operation. This study proposes a new N-channel contact coupling gate multi-time programmable non-volatile memory cell. By adding multiple coupling contacts, the coupling ratio of the floating gate can be improved without additional process step and extra masking.
The new N-channel contact coupling gate multi-time programmable non-volatile memory cell is single poly and stores charge in floating gate by channel hot electron injection, and erases by Fowler-Nordherim tunneling. The program time is within 50□s, erase time is within 150ms, endurance is up to 10K and the cell has been verified to pass the criteria after 1000 hours of retention bake at 125oC. The contact coupling’s characterization needs neither another coupling well served as an erase gate nor a select transistor in array operation. Therefore, an ultra small cell size has been demonstrated and suitable for high density application. The new cell has good operation performance, high reliability, and ultra small cell size, so it will be a promising new solution for eNVM applications.

參考文獻
[1] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech. J., vol.46, pp. 1283, 1967.
[2] D. Frohman-Bentchkowsky, “A fully - decoded 2048-Bit electrically - programmable MOS - ROM,” ISSCC Technical Digest, Feb. 1971, pp. 80-81., 1971.
[3] K. Ohsaki, N. Asamoto, I;. Takagaki, “A Single Poly EEPROM Cell Structure for Use in Standard COMS Processes” IEEE J. Solid State Circuits, Vol. 29, No. 3, March 1994, PP. 311-316.
[4] P. Kazcounian and B. Eitan, “A single-poly EPROM for custom CMOS logic applications,” IEEE Custom Integrated Circuit Conference, pp. 59-62, 1986.
[5] M.-H. Chi and A. Bergemont, “A New Single-poly FLASH Memory Cell with Low-voltage and Low power Operations for Embedded Applications,” IEEE Device Research Conference Digest, 5th, pp. 126-127, 1997.
[6] P. Pavan, R. Bez, P. Olivo, and E. Zanoni. “Flash memory cells-an overview,” Proc. IEEE, pp. 1248, 1997.
[7] S. Lai, “Flash Memories: where we were and where we are going.” IEEE IEDM Technical Digest, pp. 971, 1998.
[8] C. Hu, “Lucky-electron model of channel hot-electron emission.” IEEE IEDM Tech. Dig., p. 22, 1979.
[9] R. B. Fair and R. C. Sun, “Threshold-voltage instability in MOSFET’s due to channel hot-hole emission” IEEE Trans. Electron Devices, vol. ED-28, pp. 83-93, Jan. 1981.
[10] Fowler, R. H.; Nordheim, L., “Electron Emission in Intense Electric Fields” Proceedings of the Royal Society of London. Series A, Containing Papers of a Mathematical and Physical Character, Volume 119, Issue 781, pp. 173-181
[11] M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2,” J. Appl. Phys., vol.40, no.1, pp. 278-283, 1969.
[12] Z. A. Weinberg, “On tunneling in MOS structure,” J. Appl. Phys., vol. 53, pp. 5052, 1982.
[13] J. Peng, G .Rosendale , M . Fliesler , D. Fong , J. Wang ,C. Ng ,Zs Liu ,Harry Luan," A Novel Embedded OTP NVM Using Standard Foundry CMOS Logic Technology", IEEE 2006.
[14] Peng, Jack, et al., “Programming methods and circuits for semiconductor memory cell and memory array using a breakdown phenomena in an ultrathin dielectric, "US Patent # US 6,671,040 B2, Dec.30, 2003.
[15] Wang, R.S.C.; Shen, R.S.J.; Hsu, C.C.H., “Neobit® - high reliable logic non-volatile memory (NVM)” Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the 5-8 July 2004 Page(s):111 - 114
[16] Hsu, Charles Ching-Hsiang; Lin, Yen-Tai; Shen, Shih-Jye , “Future Prospective of Programmable Logic Non-Volatile Device” ASSCC 2006. IEEE Asian, Nov. 2006 Page(s):35 - 37
[17] C.-S Hsieh, P.-C Kuo, C.-S Chiu, C.-H Hon, C.-C Fan, W.-C Kung, Z.-W Wang, and Erik S. Jeng, “NVM Characteristics of single MOSFET cells Using Nitride Spacers With Gate-to-Drain NOI” IEEE Trans. Electron Devices, vol. 51, pp. 1811-1817, Nov. 2004.
[18] Erik S. Jeng, C.-S Chiu, C.-H Hon, P.-C Kuo, C.-C Fan, C.-S Hsieh, H.-C Hsu, and Y.-F Chen,“Performance Improvement and Scalability of Nonoverlapped Implantation nMOSFETs With Charge-Trapping Spacers as Nonvolatile Memories” IEEE Trans. Electron Devices, vol. 54, pp. 3299-3307, Dec. 2007.
[19] R. Bez, E. Camerlenghi, D. Cantarelli, L. Ravazzi, and G. Crisenza, “A novel method for the experimental determination of the coupling ratios in submicron EPROM and flash EEPROM cells” IEEE IEDM Technical Digest, pp. 99, 1990.
[20] Brand, K. Wu, S. Pan, and D. Chin, “Novel read disturb failure mechanism induced by FLASH cycling,” IEEE International Reliability Physics Symp., p. 127, 1993
[21] S. Haddad, C. Chang, B Swaminathan, and J. Lien, “Degradations due to hole trapping in flash memory cells” IEEE Electron Device Lett., vol. 10, Issue 3, pp. 117-119, 1989.
[22] R. Fastow, K. Ahmed, S. Haddad, M. Randolph, C. Huster, and P. Hom, “Bake Induced Charge Gain in NOR Flash Cells” IEEE Electron Device Lett., vol. 21, Issue 4, pp. 184-186, 2000.
[23] F. Arai, T. Maruyama, R, Shirota, “Extended data retention process technology for high reliable flash EEPROMs of 106 to 107 W/E cycles.” IEEE International Reliability Physics Symp., 1998
[24] B. De Salvo, G. Ghibaudo, G. Pananakakis, G. Guillaumot, P. Chandelier, and G. Reimbold, “A new extrapolation law for data-retention time-to-failure of nonvolatile memories” IEEE Electron Device Lett., vol. 20, Issue 5, pp. 197-199, 1999.
[25] M. Momodomi, T. Tanaka, Y. Iwata, Y. Tanaka, H. Oodiara, Y. Itoh, R. Shirota, K. Ohuchi, F. Matsuoka, “A 4-Mbit NAND-EEPROM with tight programmed Vt distribution” IEEE Journal of Solid State Circuit, vol. 26, Issue 4, 1991.
[26] K. Naruke, S. Taguchi, and M. Wada, “Stress-induced leakage current limiting to scale down EEPROM tunnel oxide thickness,” in IEDM Tech. Dig. 1988, p. 424.
[27] S. Aritome, R. Shirota, G. Hemnik, T. Endoh, and F. Masuoka, “Reliability issues of Flash memory cells,” Proc. IEEE, vol. 81, pp. 776–788, May 1993.
[28] B. Wang, M. Niest, Y. Ma, H. Nguyen, and R. Paulsen, “Scaling Tunneling Oxide to 50Å in Floating-Gate Logic NVM at 65nm and Beyond” IIRW final report, 2007.
[29] Y. Ma, T. Gilliland, B. Wang, R. Paulsen, A. Pesavento, C. H. Wang, H. Nguyen, T. Humes, and C. Diorio, “Reliability of pFET EEPROM with 70-Å tunnel oxide manufactured in generic logic CMOS processes,” IEEE Trans. Device Mater. Rel., vol. 4, no. 3, pp. 353–358, Sep. 2004.
[30] Te-Liang Lee, Yi-Hung Tsai, Wun-Jie Lin, Hsiao-Lan Yang, Chiu-Wang Lien, Chrong Jung Lin, and Ya-Chin King, “A New Differential P-Channel Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell With Self-Recovery Operation,” IEEE Electron Device Lett., Issue 99, 2011.