加法電路是所有計算機中，算數邏輯單元 ( ALU ) 的基本電路。在計算機的運算中，例如：加法、減法、乘法、除法都需要加法器的運用才能達成。加法器可將2組2進位的數字作加法的運算，是組成數位運算系統的基本邏輯元件，因此若一位數位電路的設計者想要提高設計電路的運算速度，提高加法器的運算速度，可間接的提高整個數位邏輯電路的運算速度。因此提高加法器的運算速度成為數位電路設計者競相努力的目標。
加法電路的運算速度，其主要問題在於進位傳遞的延遲時間。為了提高計算機的運算速度，在過去幾十年來，有關改進這方面問題的論文陸續被發表 [1-6,8]。如：前看進位加法器 (Carry Look-ahead Adder) [2,3,8]、進位跳躍加法器 (Carry-Skip Adder)、進位儲存加法器 (Carry Save Adder)、進位選擇加法器 (Carry Select Adder) [5,6,8] 等等。
在此我們討論過去數位電路先進們所提議的一些加法器，Ripple Carry Adder(RCA)、Carry Look-Ahead Adder(CLA) [2,3,8]、Carry Select Adder(CSA) [5,6,8] 等，此外我們亦提供一種新架構 Segmented Parallel Adder(SA) 作為加法器突破速度的另一種選擇。
本論文的架構如下：在第二章，針對目前較常使用的加法器電路作一個概略性的描述，以便與我們所提出的方法作比較。在第三章，我們提出the segmented parallel adder作為加法器的另一種選擇架構。在第四章，我們將實際模擬比較the segmented parallel adder較各種常使用加法器優越的地方。在第五章，作一個扼要的討論與心得，還有未來可能的研究方向。

The speed of a digital arithmetic processor for addition, subtraction, multiplication, and division is heavily dependent on the speed of the adders used in the system. In the system on chip (SoC) generation, faster speed and smaller area electric devices are required to build the large circuit. In order to increase the speed of ALU, increasing the speed of adders is a useful and efficient method.
This thesis proposes a segment parallel adder (SA) as a choice for various high speed addition techniques. This segment parallel adder consists of horizontal and vertical segments those are executed the addition in parallel. When the horizontal segment starts addition from the LSB to the MSB, the vertical segment is also active simultaneously from the top to the bottom such that the time delay from the top to the bottom should be equal to that of the horizontal segment of the carry propagation from the LSB to the MSB. In this way, an optimal matched addition is obtained.
From the simulation result, the proposed variable segment parallel adder reveals the fewest delay and fastest speed. The delay of the variable segmented parallel adder can be reduced to 29% compared with the CSA at the cost of larger area of 72%. The AT2 in this case is also reduced to 14%.

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