在先進通訊系統中，隨著人們對於快速以及高品質資料傳輸的要求與日俱增，高速電路設計成為一個非常重要的研究領域。在本論文中，我們利用升頻 (FOS)的技術直接提高電路的操作頻率，然而在升頻的過程中會發生 timing violation 而造成了系統 SNR的嚴重衰減。針對這一個問題，我們提出兩種解決的方法，一種是系統層面的技術，另一種是電路運算層面的技術。在系統層面，使用低精準度冗位 (RPR) 來提升電路速度同時抑制雜訊的快速增加，RPR是一種在最近被提出來應用於低功率數位電路的系統架構，其主要的原理是在系統中加入一個相對於MDSP ( Main DSP)精準度較低但是運算功能一樣的RDSP (Reduced DSP)來執行在降電壓(VOS)的情況之下，雜訊的偵測以及更正，藉以達到低功率消耗的應用，現在我們提出將此種系統架構應用於FOS之下，已達到高速電路的應用。而在電路運算層面，因為現行一般的電路運算單元的設計，是不考慮
輸入信號的強度大小，這意味著必須透過完整運算單元的計算方可以得到最後的輸出信號，也就是輸出信號的延遲時間較長，而事實上，輸出信號的產生和輸入信號是具有相關性的，因此我們提出副字組偵測 (SDP) 技術來偵測輸入信號的強度大小藉以調整電路運算的時間，換言之，SDP 能夠縮短critical path運算的延遲時間，也就能降低timing violation的產生機率。另外，SDP技術所引導出的cost overhead是非常低的，這對於IC設計而言是非常吸引人的。 最後，
基於RPR 和 SDP 技術，在FOS操作下，我們設計了一個快速傅立葉轉換 (FFT) 處理器來實現高速電路設計，實驗結果顯示當頻率提升至最大可行頻率的1.21倍時，使用RPR 和SDP技術相對於傳統單一個MDSP電路將有著34.5 dB的增進。

The high speed circuit design is an imperative issue for advanced communication systems. Because of the requirement of high speed and high quality data transmission, high speed circuit design becomes an important research field.
In the thesis, we utilize the frequency overscaling (FOS) technique to increase the operating frequency of the circuit. However, the FOS causes timing violation and degrades SNR performance greatly. In order to alleviate SNR degradation, we employ two techniques to combat the error noise generated by the timing violation. One is the system-level technique, and the other is the arithmetic-level technique.
In the system level, the reduced-precision redundancy (RPR) is used to improve the clock speed with acceptable noise increase. It employs the reduced-precision replica of main DSP module as the estimator to detect and correct the error.
In the arithmetic level, we propose a subword-detection processing (SDP) which can adjust datapth arithmetic timing by detecting the magnitude of the input signal, that is, the SDP technique can reduce the computation critical delay, and thereby result in the reduction of the probability of timing violation. Based on the RPR-based architecture and the SDP technique, we design an RPR-based SDP FFT processor to realize the high-speed DSP circuit using the FOS. The experimental results show that the SNR performance can be improved by 34.5 dB when the operating frequency is overscaled to 1.21 times of the maximal achievable frequency below which the timing violation does not exist.

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