將靜態隨機存取記憶體之操作電壓降至次臨界區域可大幅減少其功率消耗，然而一般廣泛使用的六電晶體單元之靜態隨機存取記憶體可能無法在次臨界區域成功操作。
傳統六電晶體單元於次臨界區域操作主要有三大問題，第一為抗靜態雜訊之限度隨電壓而減少，第二為寫入能力不足因電晶體驅動之電流過小，第三為讀取時過大之漏電流干擾正確之讀值，因此許多新型單元被提出以解決次臨界靜態隨機存取記憶體的操作問題。
十電晶體單元解決了次臨界靜態隨機存取記憶體所造成之操作問題，在讀取時位元線不與存值之結點直接連結加強了讀取時抗雜訊之能力並且大幅減少位元線之漏電流，寫入時抬高字元線之電壓則改善了寫入能力，但是該單元使用了較其他單元更多之面積，本論文提出之單元將原十電晶體單元之差分架構轉為單端之結構，電晶體因此降低到七，然而這將會減弱單元之寫入能力，因此切斷反饋電流之電路被加入以幫助電路寫入，此外一般之差分架構感測放大器無法用於單端之架構，故使用一無需啟動信號之單端感測放大器用來替代傳統之感測放大器。
在模擬之中，提出之單元證明有較低之漏電流相較於具有相近面積之靜態隨機存取記憶體單元並且較小的面積相對於十電晶體單元。

Scaling SRAM’s supply voltage to sub-threshold region greatly reduces power consumption. However, the conventional 6T SRAM cell does not operate in sub-threshold region well.
Conventional 6T SRAM cell has three major issues for operating in sub-threshold region. The first one is low read SNM (static noise margin) with voltage decreased. The second one is worse write ability due to weak transistor current. The third one is leakage current may interfere the read operation. Therefore, many novel cells have been proposed to solve the issues for sub-threshold SRAM [5][9][11].
This work is based on one of these cells, the 10T cell [11]. A 10T cell solved these issues caused by sub-threshold operations. But it uses more area compared to other cells. We propose a cell that changes the differential structure of 10T cell to single-ended structure, thus, reduces the cell transistor number to 7. However, it has lower write ability. Therefore, boost word-line and cut-off feedback are added to help write ability.
This cell is shown to have smaller leakage current compared to cell with similar area by simulation. It also has smaller area compared to 10T cells.

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