研究生: |
余業鑫 Yeh-Hsin Yu |
---|---|
論文名稱: |
以生產力為觀點的半導體晶圓廠產能規劃方法 A Productivity-Oriented Capacity Optimization Model for Semiconductors Manufacturing Industry |
指導教授: |
阮約翰 博士
Dr. John Yuan |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 工業工程與工程管理學系 Department of Industrial Engineering and Engineering Management |
論文出版年: | 2003 |
畢業學年度: | 91 |
語文別: | 中文 |
論文頁數: | 82 |
中文關鍵詞: | 系統模擬 、X-factor 、生產力 、產能最佳化模型 、半導體 |
外文關鍵詞: | Simulation, X-factor, Productivity, Capacity Optimization Model, semiconductor |
相關次數: | 點閱:3 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
半導體晶圓廠資本支出佔整體投資相當大的比率,因此對於一個投片數量為固定的晶圓廠來說,過多的設備投資會造成生產力下降,也無益產出量的提升。反之過少的設備投資會使產出不如預期造成收益上的損失並影響生產績效。所以本研究提出一「以生產力為觀點的晶圓廠產能規劃方法」,藉由模擬與一有效快速的尋優法則,改善模擬耗時過長的缺點並有效調整工作區機台數目,使得晶圓廠系統收益提高並使晶圓廠生產系統績效維持在一優良狀態。
本論文模式共分四大模組,分別為1.起始解模組:目的為求出各工作區機台數量起始解。2.驗證模組:目的為檢驗各起始解產能現況。3.尋優模組:目的為找出系統的優良產能狀態。4.機台微調:目的為在不影響優良產能狀態下找出系統收益更佳的各工作區機台數量。此四個模組經實例驗證後,證明能有效減少模擬次數,並提高系統收益,也證明本論文即具實用價值。
In general, the investment of manufacturing equipments in wafer fabs occupies most proportion of total investments. That is, the over-investing for equipments under a wafer fab where the releasing amount of wafer is fixed will not be helpful to raise the throughput. On the other hand, the lack of investment for equipments may result in the insufficient throughput, the loss of benefit and the terrible performance of manufacturing. In this thesis, we propose a productivity-oriented capacity optimization model to efficiently adjust the machine number in work-centers, raising the benefit of fabs and maintain the performance of manufacturing system to be in excellent status according to simulation and a fast search principal. The proposed method can be divided to four major modules, they are (a) the module of initial solution, obtaining the initial number of machines in all work-centers, (b) the module of validation, verifying the status of capacity for each initial solution, (c) the module of searching, evaluating the outstanding status of capacity in the manufacturing system, and (d) the module of adjusting, searching the better quality of solution for machine number in each work-center without violating the outstanding status of capacity. To verify the performance, a simulation model is constructed to evaluate the efficiency of out planning. The related results show that the proposed method can significantly reduce the number of simulations, raising the benefit of manufacturing system, and as well as a good tool for implementing in real world applications.
[1] R.Uzsoy , Lee C-Y, Martin-Vega LA, “A Review of Production Planning and Scheduling Models in the Semiconductor Industry. Part Ⅰ: System Characteristics, Performance Evaluation and Production planning., ” IIE Trans., Vol. 24, No. 4, 47-60 (1992).
[2] K. M. Bertthauer, “Capacity planning in Networks of Queues with Manufacturing Application.,” Mathl. Comput. Modeling, Vol. 21, No. 12, 35-46 (1995).
[3] Daniel P. Conners, Gerald E. Feigin, David D. Yao, “A Queueing Network Model for Semiconductor Manufacturing.,” IEEE Trans., Vol. 9, No. 3, 417-427 (1996).
[4] Donald P. Martin, “Key factors in designing a manufacturing line to maximize tool utilization and minimize turnaround time ,” Semiconductor Manufacturing Science Symposium, 48-53 (1993).
[5] D. Meyersodorf, Taho Yang, ” Cycle Time Reduction for Semiconductor Wafer Fabrication Facilities.,” IEEE Advanced Semiconductor Manufacturing Conference, 37-41 (1997).
[6] James T. Lin, Fu-Kwun Wang, and C. K. Wu, "Connecting Transport of Automated Material Handling System in Wafer Fab.," International Journal of Production Research, Vol. 41, No.3, 529-544 (2003).
[7]R. C. Leachman, “Close-loop Measurement of Efficiency and Equipment Capacity., ” IEEE Advanced Semiconductor Manufacturing Conference, 115-126 (1995).
[8]Rafi Maslaton, “Cycle Time Management.,” 13th Edition, Semiconductor Fabtech, 77-81.
[9]Javier Bonal, Carlos Ortega, Luis Rios, Santiago Aparicio, Manual Fernandez, Maria Rosendo, Alejandro, Sergio Malvar, “Overall Fab Efficiency.,” IEEE Advanced Semiconductor Manufacturing Conference, 49-52 (1996).
[10] W. Chou, J. Eveton, “Capacity Planning for Develop Wafer Fab Expansion.,” IEEE Advanced Semiconductor Manufacturing Conference, 17-22 (1996).
[11] Yon-Chun Chou, L-Hsuan Hong, “A Methodology for Product Mix Planning in Semiconductor Foundry Manufacturing.,” IEEE Transactions on Semiconductor Manufacturing, Vol. 13 No. 3 , 278 -285 (2000).
[12] Donald P. Martin, “How the law of unanticipated consequences can nullify the theory of constraints: The case for balanced capacity in a semiconductor manufacturing line.,” IEEE Advanced Semiconductor Manufacturing Conference, 380-385 (1997).
[13]M. Aybar, K. Potti, T. LeBaron, “Using Simulation to Understand Capacity Constraints and Improve Efficiency on Process Tools.,” Proceeding of the 2002 Winter Simulation Conference, 1431-1435 (2002).
[14]Ming-Hsin Hung, Edward Wang, Ivan Wang, “Using Simulation and Daily-Demand Method to Analyze the Capacity Utilization fpr Product-Mix in Semiconductor Fabrication., ” Semiconductor Manufacturing Technology Workshop, 302 -306(2002)。
[15] D. R. Plane, “Discrete optimization.” Prentice-Hall, Englewood Cliffs, N.J., (1971).
[16] Mikell P. Groover, ”CAD/CAM :computer-aided design and manufacturing.,” Prentice-Hall, Englewood Cliffs, N.J., (1984).
[17] Van Zant Peter, “Microchip fabrication :a practical guide to semiconductor processing.,” 4th ed. McGraw-Hill, New York, (2000).
[18] William J. Stevenson, ”Production/ operations management,” 6th ed., Irwin, Boston, (1999).
[19] Hong Xiao, “Introduction to Semiconductor Manufacturing Technology” N.J.,Prentice Hall(2001).
[20] 網頁資料: http://www.amt.com.tw/product/product_1.html.